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Wafer demand for ‘More than <span style='color:red'>Moore</span>’ devices to grow by 10%

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Wafer demand for ‘More than Moore’ devices to grow by 10%

Wafer demand for ‘More than Moore’ (MtM) devices is expected to grow by 10% between 2017 and 2023, Yole Développement, the market research and strategy consulting company, reports.Driven by the adoption of evermore electronic components in end products, the semiconductor industry is facing a new era, Yole claims. Device scaling and cost reduction will no longer continue on the path followed for the past few decades. Instead, semiconductor companies are seeking solutions that bridge the gap between cost and performance, whilst adding increased functionality through integration.MtM devices (including MEMS & sensors, CMOS Image Sensors, power electronic, along with RF devices) represent this functional diversification of technologies, the report continues, combining performance, integration and cost - not limited to CMOS scaling. And their importance, Yole predicts, will become greater.MtM devices reached almost 45million 8-inch eq wafers in 2017 and the demand is anticipated to reach more than 66m 8-inch eq wafers by 2023.According to the report, 6-inch and 8-inch are forecast to represent more than 60% of MtM wafers' total wafer consumption. However, Yole says 12-inch will represent the fastest growth between 2017 and 2023, with demand growing from 3.3m units to 7.5m by 2023. This is due mainly to Backside Illumination CMOS Image Sensors (BSI CIS) (3D stacked BSI, 3D hybrid BSI), Yole adds.Currently, 4-inch wafer diameter is in large demand for MtM applications driven by RF Surface Acoustic Wave filter products. However, Yole says the adoption of this wafer will decrease due to a transition to 6-inch.Despite silicon's dominance in the semiconductor area (80% market share), alternative substrates, such asSiGe, GaAs, GaN, and SiC,are disrupting the MtM market.Yole suggests that the ‘megatrend’ market is driving the MtM wafer volume evolution. These megatrends include 5G, mobile, voice processing, smart automotive, augmented reality/virtual reality, and artificial intelligence.Driven by the increasing deployment of renewable energy sources (principally solar energy inverters) and industrial motor drives, as well as the growing electric and hybrid vehicles (EV/HEVs) automotive industry, power devices’, Yole anticipates the wafer market size to grow at an almost 13% CAGR between 2017 and 2023.

Key word：

Wafer

Release time：2018-06-29 00:00 reading：1301 Continue reading>>

DARPA Heeds <span style='color:red'>Moore</span>’s Wisdom

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DARPA Heeds Moore’s Wisdom

　　Gordon Moore, whose eponymous law has guided the industry for decades, supplied the ideas behind the Defense Advanced Research Projects Agency’s newly announced additions to its Electronics Resurgence Initiative (ERI), according to Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO). DARPA this week posted three broad agency announcements (BAAs) that describe six new programs to address the problems that Moore 50 years ago predicted would loom at the end of the current silicon roadmap. The programs will collectively add $75 million a year to the ERI’s cost, bring the projected annual tally for the four-year initiative to $216 million. The agency is calling the new programs its Page 3 Investments as a tribute to Moore, who described the research challenges on page 3 of “Cramming More Components onto Integrated Circuits,” published in Electronics in April 1965 and excerpted here.　　Heat Problem　　Will it be possible to remove the heat generated by tens of thousands of components in a single silicon chip?　　If we could shrink the volume of a standard high-speed digital computer to that required for the components themselves, we would expect it to glow brightly with present power dissipation. But it won’t happen with integrated circuits. Since integrated electronic structures are two dimensional, they have a surface available for cooling close to each center of heat generation. In addition, power is needed primarily to drive the various lines and capacitances associated with the system. As long as a function is confined to a small area on a wafer, the amount of capacitance which must be driven is distinctly limited. In fact, shrinking dimensions on an integrated structure makes it possible to operate the structure at higher speed for the same power per unit area.　　Day of Reckoning　　Clearly, we will be able to build such component-crammed equipment. Next, we ask under what circumstances we should do it. The total cost of making a particular system function must be minimized. To do so, we could amortize the engineering over several identical items, or evolve flexible techniques for the engineering of large functions so that no disproportionate expense need be borne by a particular array. Perhaps newly devised design automation procedures could translate from logic diagram to technological realization without any special engineering. It may prove to be more economical to build large systems out of smaller functions which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.　　Linear Circuitry　　Integration will not change linear systems as radically as digital systems. Still, a considerable degree of integration will be achieved with linear circuits. The lack of large- value capacitors and inductors is the greatest fundamental limitation to integrated electronics in the linear area.　　By their very nature, such elements require the storage of energy in a volume. For high Q it is necessary that the volume be large. The incompatibility of large volume and integrated electronics is obvious from the terms themselves. Certain resonance phenomena, such as those in piezoelectric crystals, can be expected to have some applications for tuning functions, but inductors and capacitors will be with us for some time.　　The integrated RF amplifier of the future might well consist of integrated stages of gain, giving high performance at minimum cost, interspersed with relatively large tuning elements.　　Other linear functions will be changed considerably. The matching and tracking of similar components in integrated structures will allow the design of differential amplifiers of greatly improved performance. The use of thermal feedback effects to stabilize integrated structures to a small fraction of a degree will allow the construction of oscillators with crystal stability.　　Even in the microwave area, structures included in the definition of integrated electronics will become increasingly important. The ability to make and assemble components small compared with the wavelengths involved will allow the use of lumped parameter design, at least at the lower frequencies. It is difficult to predict at the present time just how extensive the invasion of the microwave area by integrated electronics will be. The successful realization of such items as phased-array antennas, for example, using a multiplicity of integrated microwave power sources, could completely revolutionize radar.　　According to Chappell, the ERI program will “stand on the shoulders of Moore” by extending his principles to ensure continuance of “the greatest commercial benefits and the greatest gains in defense capabilities” ever achieved.　　Chappell believes that Moore’s Law can be extended indefinitely by DARPA’s ERI initiatives, which already address materials and integration, circuit design, systems architecture, and strengthening of the fundamental-research base.　　The agency’s new Three Dimensional Monolithic System-on-a-Chip (3DSoC) program will aim at a fiftyfold improvement in computation time, while using less power, by packing processors, logic, memory, and input/output in power-saving, high-riser three-dimensional cubes. A second program, funded under the same BAA as the 3DSoC initiative, is Foundations Required for Novel Computers (FRANC), which will scrap John von Neumann’s separate data and memory functions. According to DARPA, combining data and memory functions will “overcome the memory bottleneck” of moving data from memory to the processor and back again. The effort will require development of novel materials, such as memristors; components, such as artificial neurons and synapses; and algorithms, including ones modeled on the human brain.　　The second new BAA is a two-pronged effort to redefine circuit and system specialization. The Intelligent Design of Electronic Assets (IDEA) program will look to automate design so that even nonengineers can describe the functions to be performed, with a robotic design automation system doing the work to create the design overnight. The Posh Open Source Hardware (POSH) program will support a complementary open-source verification framework to check and redesign, if necessary, even the most complicated systems-on-chip and printed-circuit boards produced by IDEA.　　The third BAA likewise comprises two programs. Software Defined Hardware (SDH) will act as a “decision assistant” for reconfigurable hardware/software that will run data-intensive algorithms for artificial-intelligence applications using application-specific ICs to handle the thousands of intelligence, surveillance, and reconnaissance sensors used in modern warfare as well as civilian Big Data applications. The complementary Domain-Specific System-on-a-Chip (DDSoC) program aims to develop multi-application hardware/software systems that users could mix and match to solve problems such as software-defined radio, which encompasses mobile communications, satellite communications, personal area networks, and all types of radar. SDR applications will emerge for electronic warfare between 2025 and 2030, according to Chappell.　　For more details, see DARPA’s slide deck on the six new directions for the ERI program.

Key word：

DARPA

Release time：2017-09-18 00:00 reading：1425 Continue reading>>

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DARPA Calls for Post-Moore Ideas

　　It’s “the summer of listening” for Bill Chappell, head of a $200+ million government program seeking ways to revitalize electronics. He doesn’t expect to find a replacement for Moore’s law, but he does hope to “shake things up,” creating a handful of alternatives for advancing semiconductor performance.　　“I don’t think exponential growth on a single variable [such as CMOS scaling] is achievable,” Chappell said in an interview about the Electronics Resurgence Initiative (ERI).　　“The next era we're heading into is about progress in lots of variables…hardware/software co-design, new materials and functional blocks, specialization for each app…We’re not out of ideas at all, this is a wildly interesting time where lots of creativity will make up for the march of scaling,” said Chappell, director of the microsystems group at the Defense Advanced Research Projects Agency (DARPA).　　Many industry executives heard about ERI for the first time at a June meeting Chappell hosted in Austin during the Design Automation Conference. About 60 people attended the meeting from companies including Analog Devices, ARM, Cadence, IBM, Intel, Qualcomm, Synopsys, TSMC and Xilinx.　　“It was an intro to the program for industry leaders who may not have been involved with DARPA,” said Steve Keckler, a vice president of architecture research at Nvidia, who spoke at the event about the GPU designer’s work with the agency.　　“I see ERI as an opportunity to engage a broader set of partners to bring things to market, many who haven’t collaborated with DARPA before,” Keckler said.　　This week DARPA conducted a two-day meeting in San Jose to work with chip experts and help them form partnerships. As many as 300 people attended, representing about 45 companies, 10 defense contractors and numerous universities.　　“This is the start of something with teeth behind it,” Chappell said during a break in the event.　　Earlier, DARPA hosted a meeting with defense contractors in Washington D.C. to spawn their ideas. A team of ERI program managers will package the best concepts into a formal call for proposals in September. DARPA will pick and negotiate contracts on winning projects over the following seven months before funding is released and the hard work begins.

Key word：

DARPA

Release time：2017-07-21 00:00 reading：1079 Continue reading>>

U.S. Seeks Life After <span style='color:red'>Moore</span>’s Law

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U.S. Seeks Life After Moore’s Law

　　A few dozen executives will gather next week at the first event to kick off what could become nearly a half billion dollar program to revitalize the U.S. electronics industry. An event the following week in Silicon Valley will seek input from the broader tech community on finding new materials, architectures and design processes for a post-Moore’s-law era.　　The Electronics Resurgence Initiative (ERI) under the Defense Advanced Research Program Agency aims to serve the needs both of the military and the tech industry. DARPA will spend a total of $200 million on the effort including $75 million of new funding expected in its fiscal 2018 budget.　　There’s no “specific requirement for industry cost share, but…it should scale with the value of the effort to the company's commercial business…[and] we think a 1:1 cost share would be appropriate,” Bill Chappell, director of DARPA's microsystems technology office that oversees the program, said in an email exchange.　　DARPA will boil feedback from the events into a call for proposals it will release in September. Each accepted project will have its own schedule and deliverables, but DARPA projects generally last four years.　　The spending is significant but relatively small compared to the ambitions of the program. It aims to accelerate research in the kinds of post-Moore’s law areas Gordon Moore himself defined in his article that defined chip scaling.　　They include “the integration of novel materials and functional blocks, automation in design, and the reuse of large functional blocks and architectures,” DARPA said on its ERI Web site.　　The two July events will prime the pump for proposals and investments for ERI from industry and academia. The head of the Semiconductor Industry Association applauded the effort in a blog post last month, but noted it comes amid proposed cuts in other semiconductor-related efforts and agencies.　　The July 11 summit in the Washington D.C. area is limited to 65 executives mainly drawn from defense contractors who will implement new technologies as part of project proposals. A two-day workshop in San Jose July 18-19 aims to gather “community input on vision, goals, and metrics for research and development investments,” the invitation said.　　At both events, DARPA and industry partners will share the program’s outline and details of how to make proposals. The events are also networking opportunities to find partners. In addition, attendees will be able to give DARPA program managers a five-minute pitch of their proposals at the San Jose event.

Key word：

U.S., Moore

Release time：2017-07-05 00:00 reading：1162 Continue reading>>

<span style='color:red'>Moore</span>’s Law’s End Reboots Industry

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Moore’s Law’s End Reboots Industry

　　The expected death of Moore’s Law will transform the semiconductor and computer industries, said a panel of experts at an event marking the 50th anniversary of the Alan Turing award.　　A basket of silicon, systems and software technologies will continue progress, but not at the same pace, they said. With no clear replacement for CMOS scaling, semiconductor and systems industries may be reshaped into vertical silos, they added.　　“Moore’s Law said transistor density doubles every 18 months, something we maintained for 25 years, but it began slowing down to every two to three years around 2000-2005, and more recently we’re seeing doubling about every four years, so were reaching the end of semiconductor technology as we know it,” said John Hennessy, former president of Stanford University and author of a key text book on microprocessors.　　Dennard scaling, a related observation that energy requirements scale as silicon shrinks, “already has been non-operational for 10-15 years, creating an era of dark silicon where we quickly turned to multicore processors,” Hennessy added.　　Moore’s Law is really an observation about economics, not a law of physics. The question is whether we can find another aspect of physics that has a return on investment like CMOS, said Margaret Martonosi, a systems specialist at Princeton.　　Insofar as “Moore’s Law is about a rate [of density scaling], it is dead because I think we are at the end of a predictable rate and in a few generation we’ll hit the limits of physics,” said Doug Burger, a distinguished engineer working on FPGA accelerators at Microsoft’s Azure cloud service.　　“Moore’s Law gave us a free ride and that’s just about over so we are entering a wild, messy time and it sounds like a lot of fun,” Burger said.　　“I think we still have a few more years” of CMOS scaling, said Norm Jouppi, a veteran microprocessor designer and lead of the team behind Google’s TPU accelerator. “Some apps will continue to see performance speed ups for next a decade but for others they will come more slowly,” he said.　　Jouppi quipped that the industry is in denial about Moore's Law, like the vendor in the Monty Python dead-parrot sketch, who insists a bird is “not dead, it’s just resting.”

Key word：

Moore, Reboots Industry

Release time：2017-06-27 00:00 reading：1026 Continue reading>>

Nvidia CEO Says <span style='color:red'>Moore</span>’s Law Is Dead

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Nvidia CEO Says Moore’s Law Is Dead

　　Nvidia CEO Jensen Huang has become the first head of a major semiconductor company to say what academics have been suggesting for some time: Moore’s Law is dead.　　Moore’s Law, named after Intel cofounder Gordon Moore, reflects his observation in 1965 that transistors were shrinking so fast that every year twice as many could fit onto the same surface of a semiconductor. In 1975, the pace shifted to a doubling every two years.　　The enablers of an architectural advance every generation — increasing the size of pipelines, using superscalar tweaks and speculative execution — are among the techniques that are now lagging in the effort to keep pace with the expected 50 percent increase in transistor density each year, Huang told a gathering of reporters and analysts at the Computex show in Taipei.　　“Microprocessors no longer scale at the level of performance they used to — the end of what you would call Moore’s Law,” Huang said. “Semiconductor physics prevents us from taking Dennard scaling any further.”　　Dennard scaling, also known as MOSFET scaling, is based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named. Originally formulated for MOSFETs, it states, roughly, that as transistors get smaller their power density stays constant, so that power use stays in proportion with area.　　The diminishing returns from Moore’s Law and Dennard scaling have seen the semiconductor industry enter a mature stage in which just a handful of chipmakers can afford the multibillion dollar investments required to push the process technology forward. By now, only a few chip designers have the deep pockets to double down on fabricating silicon at the 16nm and 14nm nodes, design rules where the distinction has become increasingly blurred.　　That stagnation in the progress of technology has also led to rapid industry consolidation in recent years that’s resulted in a flurry of multi-billion dollar mergers and acquisitions.　　Even so, Huang suggested a modus vivendi for the semiconductor industry that plays into graphics processors, the products that Nvidia expects will enable continuing advances for years to come. Deep learning will use the processing power of GPUs that Nvidia makes as part of a new architecture that will take the company into artificial intelligence, outside the computer gaming business Nvidia has dominated, according to Huang.　　The semiconductor industry is exploring a number of pathways beyond Moore’s Law. Some upstart Chinese chipmakers are taking a stake in Fully Depleted Silicon-On-Insulator FD-SOI. Others see a future in going beyond planar design to three-dimensional chips.　　Nvidia’s bet on artificial intelligence to take the silicon industry forward is bullish, according to Randy Abrams, an analyst with Credit Suisse in Taipei.　　Nvidia has highlighted its Volta GPU on 12nm at an 815mm die size, taking up the same surface area as 7 iPhone processors, and connected to 16GB of high bandwidth memory using Taiwan Semiconductor Manufacturing Co.’s (TSMC) silicon interposer technology. A configuration of eight of these chips in Nvidia’s DGX-1 deep learning / high performance computing machine sells for $149,000.

Key word：

Nvidia,Moore

Release time：2017-06-02 00:00 reading：1176 Continue reading>>

model	brand	Quote
MC33074DR2G	onsemi
BD71847AMWV-E2	ROHM Semiconductor
CDZVT2R20B	ROHM Semiconductor
TL431ACLPR	Texas Instruments
RB751G-40T2R	ROHM Semiconductor

model	brand	To snap up
BU33JA2MNVX-CTL	ROHM Semiconductor
ESR03EZPJ151	ROHM Semiconductor
TPS63050YFFR	Texas Instruments
BP3621	ROHM Semiconductor
STM32F429IGT6	STMicroelectronics
IPZ40N04S5L4R8ATMA1	Infineon Technologies

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