<span style='color:red'>B’com</span>’s Jericho2 Rides 2.5D Stack
  Broadcom’s latest communications processor rides a 2.5D chip stack with HBM2 memory. Jericho2 uses the boost in memory bandwidth to leapfrog the performance of OEM ASICs in high-end switches and routers.  The chip expands into networking the packaging technology pioneered by AMD, Nvidia, and Xilinx in high-end FPGAs and graphics processors. With its StrataDNX Jericho2, Broadcom also takes a small step toward open-programming environments by providing C++ tools for the chip to select customers.  The 16-nm processor, announced Tuesday (March 6), packs a whopping 208 50-Gbits/s PAM4 SerDes to deliver 10 Tbits/s of aggregate throughput, supporting up to 36 400-Gbits/s Ethernet links. It leads a wave of high-end networking devices aiming to enable 400-Gbits/s links in telcom core networks and large data centers.  The HBM2 stack provides eight times the memory bandwidth of the external DRAM used in Broadcom’s previous 28-nm chip. It leapfrogs the performance of Nokia’s FP4, the current king of in-house networking ASICs.  Jericho2 is “a big deal as updates go,” said Bob Wheeler, analyst with the Linley Group. “It’s a major new generation … [that uses HBM and 2.5D] to remove the memory bottleneck.”  While Jericho2 was Broadcom’s first merchant chip to ride a 2.5D stack, the company helped design similar products as machine-learning ASICs for unnamed customers, said Oozie Parizer, a marketing manager for Jericho2. Indeed, Intel’s Nervana uses a 2.5D stack as does an AI training processor expected from startup Graphcore.  Despite the still-costly nature of 2.5D chip stacks, Broadcom expects that the chip will power OEM systems by the end of the year priced at a relatively low $1,000 per 400-GbE port.  Parizer called on memory vendors to lower the prices of their HBM stacks “to make this more of a commodity market because this is the future in networking and high-end processing. Our advances in processors have been on the order of 5x in two years, but they have not been matched by advances in DRAM.”  The chip is now sampling to customers with devices running in the lab with HBM2 modules running at target speed. Broadcom expects that it will be in production in nine to 12 months.  Broadcom will let select customers program the network pipeline of Jericho2 using C++-based tools that the company developed to automatically generate microcode. The tools mark a small step toward the kind of software-defined networks that carriers and large data center operators have been requesting for years.  The Open Networking Foundation, a trade group of carriers and web giants, demonstrated last month comms systems from multiple companies managed in software using the open-source P4 language. ONF is asking vendors to adopt P4, originally launched by startup Barefoot Networks, which makes a rival network switch called Torfino.  Broadcom is resisting the push to P4. Most OEMs and end users do not need to program processor pipelines, and Broadcom’s C++ tools are adequate for the job, said Parizer.  Programming Jericho2 “requires deep understanding and a large team to own it, handle regressions, and deal with not breaking other apps — it’s not the recommended path,” said Parizer, noting that such work takes significant time.  “We object to the concept that P4 is open. It’s controlled by one silicon vendor, while we enable a more open and powerful language … There’s a lot of hype around P4, but most customers don’t require it.”  The Broadcom tools let developers define new pipeline stages and expand address-lookup tables. “This is real future-proofing and the heart of a programmable device,” he said.  Broadcom also released a second chip, called Ramon, that can be used to link multiple Jericho2 chips in a large switch or router, potentially spanning multiple chassis.  Cisco demonstrated a Jericho chip working with one of its largest routers. Broadcom expects that many other large OEMs and data center operators will adopt it.  Broadcom quoted a dozen potential customers praising Jericho2 in a press release. They included China’s three carriers as well as AT&T, Verizon, and Tencent and OEMs such as Arista, Huawei, and ZTE.  The previous 28-nm Jericho chip was announced in March 2015. The technology comes from the high-end switch fabric chips designed by startup Dune Networks that Broadcom acquired in late 2009.  Jericho is one of a trio of high-end comms chips that help the company dominate Ethernet networking. The other two are Tomahawk, upgraded in December, and Trident, upgraded in July.
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Release time:2018-03-07 00:00 reading:1229 Continue reading>>
Q’comm Rejects <span style='color:red'>B’com</span> Board, But Analysts Bullish
  Qualcomm officially rejected Broadcom’s proposed 11-director board, setting a showdown on the semiconductor industry’s largest merger to date for the Qualcomm annual stockholders’ meeting March 6.  While Qualcomm remains adamantly against the deal, Wall Street analysts are already crunching the numbers. They are generally bullish on the deal and on Broadcom after a strong quarterly report earlier this month.  In a press statement, Qualcomm said the board members proposed by Broadcom and its private equity partner, Silver Lake, “are inherently conflicted and would not bring incremental skills or expertise to the Qualcomm board.” Broadcom’s initial $70/share bid “dramatically undervalues Qualcomm and is not actionable due to its significant regulatory uncertainty, which may not be resolved for 18 months, if ever,” it added.  In an SEC filing it proposed continuing its current board of 11 with nine outside directors including a former chairman of American Airlines, a former U.S. Ambassador to China, a former Secretary of State in Spain and chief executive of Palo Alto Networks. Qualcomm CEO Steve Mollenkopf and former CEO Paul Jacobs, who chairs the board, would continue as directors.  If Broadcom fails to convince shareholders to vote for its proposed board, it is expected to increase its bid to $77/share, according to a December 7 note from Canaccord Genuity financial analysts. It calculated generally positive scenarios of bids at five levels ranging up to $100/share.  The analysts estimated the combined company would generate $56 billion in revenues and $14.8 billion in profits in fiscal year 2018 if the deal includes Qualcomm’s proposed acquisition of NXP. Without NXP, it forecast 2018 combined revenues of $46 billion and profits of $13.6 billion.  In either case, it assumed cost reductions of $750 million in 2018 and $1.5 billion in 2019. It also assumed Qualcomm would make $500 million in cuts at NXP if that deal is approved.  “There is the potential for Broadcom to help settle licensing disputes with Apple in a more timely manner than Qualcomm might, given Broadcom’s strong relationship with Apple, and…the very strong position held by Broadcom's switching/routing chipset business with key vendors including Cisco could prove an important beachhead in the datacenter market for Qualcomm's new ARM-based server offerings,” it said.  Separately, Morgan Stanley issued a Dec. 21 report noting among other items that Broadcom has an emerging ASIC business in machine learning it expects could be “approaching $500 million in revenue in the next 2-3 years.” Morgan Staley also acts as an advisor to Broadcom in its move to acquire Qualcomm.
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Release time:2017-12-26 00:00 reading:1355 Continue reading>>
<span style='color:red'>B’com</span> Shifts Switch to 12.8 Tbits/s
  Broadcom is sampling a 12.8 Tbit/second Ethernet switch chip targeting large data centers. The news shows the company continues to set the pace for a growing pack of competitors angling for a piece of one of the most demanding markets in networking.  The Tomahawk-3 packs twice the aggregate bandwidth of the Tomahawk-2 launched 14 months ago, both made in the same 16FF+ TSMC process. The company used engineering cleverness to pack 256 56-Gbit PAM-4 serdes in an “incrementally larger” die than the T2 that used as many 25G serdes.  In recent years, the Ethernet switch market has attracted seven merchant players. At least one of them, startup Innovium, aims to sample its own 12.8 Tbit/s chip within weeks.  Broadcom dominates the market today with a 73 to 94 percent share, depending on how market watchers slice the sector valued at nearly a billion dollars. Its closest rival, Cisco Systems, takes most of the rest with systems using its own ASICs. Juniper, Hewlett Packard Enterprise and Huawei also make Ethernet switch ASICs for their systems.  Increasingly the dozen largest data center operators — including the likes of Facebook and Google — build their own switch systems or specify systems built by ODMs. They can drive sales of millions of chips a year but demand maximum bandwidth at minimum cost and power consumption.  Rising data traffic drives their need for bandwidth. The advent of machine learning and discrete flash storage servers is further fueling the Web giants’ need for fast networks, Broadcom said.  The Tomahawk-3 is geared for the next-generation of their top-of-rack and aggregation switches, delivering up to 128 100GE or 32 400GE ports, the first merchant chip to support 400GE rates. While Broadcom declined to give many specifics about this chip, it did say its delivers 100GE at 40 percent less power and 75 percent lower cost than the prior part.  The chip is “a major achievement,” said Bob Wheeler, a senior analyst with The Linley Group.  “The new Broadcom has been surprisingly aggressive — it has actually increased its high-end product cadence. They are investing in three different switch architectures — Tomahawk, Trident, and Jericho — leaving few openings for competitors,” Wheeler said.  With seven merchant chips in the pipeline and four in-house ASICs in the works, “we will see a record number of unique platforms ship in 2018, not only those based on 50 Gbit/s lanes,” said Alan Weckel, principal of market watcher 650 Group.  “There will be over one dozen unique silicon offerings for the data center by the end of 2018, shattering any previous record by a significant amount,” Weckel said.  “Back in the day every switch company did their own ASIC, then they all went merchant with really just Broadcom, and now we are back to massive ASIC diversity again,” he added, pointing to the four OEMs designing their own chips.  Expect some designs to fall by the wayside, said Sameh Boujelbene, a senior research director at Dell’Oro Group Inc.  “I don’t think the market can support this many merchant silicon vendors. I think two or three years from now we probably should see only two or three in that space,” Boujelbene said.  Among the merchant players, “only Cavium and Mellanox are really shipping in volume in 2017,” said Weckel. Marvell, China’s Centec and Taiwan’s Nephos are generally aiming at midrange and low-end markets.  A year ago, Cavium claimed it had just started shipping its 3.2 Tbit/s XPliant switch chip and had eight OEM design wins including ones at Arista and Brocade, now part of Broadcom. Mellanox’s chips generally support Ethernet and Infiniband but are mainly used in its own systems.  A representative for startup Barefoot Networks said it is in production of its Tofino chips that deliver 1.9 to 6.5 Tbits/s with white-box systems shipping since April from Edge-Core, WNC and Inventec. Customer annucements from OEMs and end users will come “in the near future,” it said.  “Definitely, Cavium and Barefoot are making most of the headlines in terms of design wins so far. However, we have yet to see whether these design wins are for large-scale deployment or just to put pressure on Broadcom,” said Boujelbene.  All the rivals except Nephos, a Mediatek spinoff, buy serdes from Broadcom’s Avago division. “When I met with Nephos, they were definitely laser focused on landing design wins with large cloud service providers such as Amazon,” he added.  Nephos came out of stealth mode in March with a 3.2 Tbit/s chip and plans for a 6.4 Tbit/s chip using die stacked with TSMC’s InFO packaging. Innovium announced its plans for a 12.8 Tbit/s chip a week later.  Innovium has “active design engagements” with OEMs, ODMs and cloud providers it expects will roll systems in early 2018 about the same time as those using the Tomahawk-3, said Amit Sanyal, vice president of product marketing for the startup. It claims its chip will deliver better “buffering, line-rate programmability, latency, performance/watt and analytics/telemetry” than Broadcom.  Wheeler of the Linley Group expects the competition will drive Ethernet switch costs from about $60/port today to about $36/port by 2020.  Rochan Sankar, a senior director of product marketing at Broadcom, disagrees. He notes the new chip will pack into a 1U system the capabilities of an 8U system designed by Facebook using 12 Tomahawk-1 chips.  “I actually think competition hasn’t been driving a lot of disruption in pricing…we’re delivering leadership economics already,” Sankar said.  Despite a reputation for cost cutting under new CEO Hock Tan, the Ethernet switch business is “one of several sustainable franchises where we are leaders…We continue to out-invest all our merchant competitors combined despite a recent influx of interest in Ethernet switching,” he added.  Barefoot and Cavium claim a software edge because they support programmable engines that can readily add new protocols as they emerge. Their work is part of a move supported by giants including AT&T and Google to software-defined networks that are easier to manage.  Data center giants “are driving their own code and programmable capabilities as close to the server as possible,” said Broadcom’s Sankar. Thus, the company has added programmability to its lower-end Trident and Jericho switches targeting carriers and business users and so-called control-plane networks.  At the high end of data-plane nets, big data centers “want performance per cost and per power,” the focus for Tomahawk. “For the top 15 to 20 cloud providers in the world performance and opex/capex efficiency are higher priorities than programmability,” he added  Tomahawk-3 packs a Gbit of memory, the most of any Broadcom switch to date. Engineers designed a new block for the chip enabling a shared buffer for RDMA-aware traffic scheduling, a key to the chip’s performance.  The design also focuses on reducing what users call tail latency, the time it takes the last packets of a flow to pass through the switch. The chip also packs a laundry list of optimizations for routing, load balancing, telemetry and other functions.
Release time:2017-12-21 00:00 reading:1174 Continue reading>>

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