台积电披露3nm工艺：晶体管密度达每平方毫米2.5亿个，性能较5nm提升7%

Release time：2020-04-20
author：AMEYA360
source：与非网
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　　台积电终于披露了 3nm 工艺的细节，在 3nm 节点上，晶体管密度将达到每平方毫米 2.5 亿个。

　　台积电首席执行官确认 3nm 节点的开发正在按计划进行，计划于 2021 年进行风险生产，并于 2022 年下半年开始批量生产。此外，台积电决定 3nm 采用 FinFET 晶体管技术。

台积电披露3nm工艺：晶体管密度达每平方毫米2.5亿个，性能较5nm提升7%

　　图源：WikiChip Fuse

　　作为参考，采用台积电 7nm EUV 工艺的麒麟 990 5G 尺寸 113.31mm，晶体管密度 103 亿，平均下来是 0.9 亿 /mm，这也意味着 3nm 制程工艺的晶体管密度将是 7nm 的 3.6 倍。这个密度形象化比喻一下，就是将奔腾 4 处理器缩小到针头大小。

　　性能方面，台积电 5nm 相对于 7nm 提升 15%，能耗比提升 30%;而 3nm 较 5nm 性能提升 7%，能耗比提升 15%。

　　此外，台积电表示 3nm 工艺研发符合预期，且并未受到疫情影响，预计在 2021 年进入风险试产阶段，2022 年下半年量产。不过，3nm 首发依然会是 FinFET 技术，因为台积电在评估多种技术之后认为 FinFET 工艺在成本及能效上表现更佳。

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