SIT Announced a Dual Channel Local <span style='color:red'>Interconnect</span> Network (LIN) Transceiver--SIT1022Q
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SIT Announced a Dual Channel Local Interconnect Network (LIN) Transceiver--SIT1022Q

　　SIT1022Q is a dual channel Local Interconnect Network (LIN) physical layer transceiver that is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, ISO 17987-4:2016 (12V) and SAE J2602 standards. It is mainly suitable for in-vehicle networks with a transmission rate of 1kbps to 20kbps.       SIT1022Q controls the state of the LINx bus through the TXDx pin, and can convert the data stream sent by the protocol controller into a bus signal with the best slew rate and waveform shaping to minimize electromagnetic radiation emission (EME). The LIN bus output pin has an internal pull-up resistor. Only when used as a master node, the LIN bus port needs to be pulled up to VBAT through an external resistor in series with a diode. SIT1022Q receives the data stream on the bus through the LINx pin, and transmits the data to the external microcontroller through the receiver’s output pin RXDx.　　SIT1022Q can operate from 5.5V to 18V and supports 12V applications. SIT1022Q has an extremely low quiescent current consumption in sleep mode and standby mode. It can quickly minimize power consumption in the event of a failure. The device can be placed in normal mode via a signal on the pin SLP_Nx.　　PIN CONFIGURATION　　FEATURE　　Compliant with LIN 2.x/ISO 17987-4:2016 (12V)/SAE J2602　　Compatible with K line　　Integrated over-temperature protection function (thermal shutdown)　　Integrated dominant time out function　　Integrated bus pull-up slave termination resistor　　Bus current limiting protection　　Supply undervoltage detection　　Very low power consumption in sleep mode and standby mode　　Support LIN bus remote wake-up　　LIN data transmission rate up to 20kbps　　Available in SOP14 and DFN4.5×3-14 packages
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Release time：2023-01-03 15:44 reading：2866 Continue reading>>
Choosing The Right <span style='color:red'>Interconnect</span>
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Choosing The Right Interconnect

　　Efforts to zero in on cheaper advanced packaging approaches that can speed time to market are being sidetracked by a dizzying number of choices.　　At the center of this frenzy of activity is the interconnect. Current options range from organic, silicon and glass interposers, to bridges that span different die at multiple levels. There also are various fan-out approaches that can achieve roughly the same high performance and low-power goals as the interposers and bridges.　　What’s driving all of this activity is a recognition that the economic and performance benefits of shrinking features are dwindling. While this has been apparent on the analog side for some time, it’s now beginning to impact ASICs for a different reason—the immaturity of applications for which chips are being designed.　　In artificial intelligence, deep learning and machine learning, which collectively represent one of the hot growth markets for chips, the training algorithms are in an almost constant state of flux. So are the decisions about how to apportion processing between the cloud, edge devices and mid-tier servers. That makes it far more difficult to commit to building an ASIC at advanced nodes, because by the time it hits the market it already may be obsolete.　　The situation is much the same in the automotive segment, where much of the technology is still in transition. And in burgeoning markets such as medical electronics, augmented and virtual reality, IoT and IIoT, no one is quite sure what architectures will look like or where the commonalities ultimately will be. Unlike in the past, when chipmakers vied for a socket in a mobile phone or a PC or server, applications are either emerging or end markets are splintering.　　That has helped push advanced packaging into the mainstream, where there are several important benefits:Performance can be improved significantly by routing signals through wider pipes—TSVs, bridges or even bonded metal layers, rather than thin wires.Distances between critical components can be reduced by placing different chips closer to each other rather than on the same die, thereby reducing the amount of energy required to send signals as well as the time it takes to move data.Components can be mixed and matched from multiple process nodes, which in the case of analog IP can be a huge time saver because analog circuitry does not benefit from shrinking features.　　Still, advanced packaging adds its own level of complexity. There are so many options in play in the packaging world that it isn’t clear which approaches will win. The outcome depends largely on the choice of interconnect, which serves as the glue between different chips.　　“The key here is the shorten the time to development, particularly for AI,” said Patrick Soheili, vice president of business and corporate development at eSilicon. “On one side, you can’t afford not to do the chip right away because you can’t be left behind. But you also have to worry about future-proofing it. The goal is to get both.”　　DARPA has been pushing chiplets as a way to standardize the assembly of components. The first commercial implementation of this sort of modular approach was developed by Marvell Semiconductor with its MoChi architecture. Marvell still uses that internally for its own chips, which it can customize for customers using a menu of options. DARPA’s CHIPS program takes that one step further, allowing chiplets from multiple companies to be mixed and matched and combined through an interposer.　　“Chiplets are absolutely part of the solution,” said Soheili. “But this isn’t so easy. If a 7nm ASIC has to sit in the middle and connect to 180nm chiplets, something has to line up the data and send it over a link.”　　Different types of interposers　　As companies working with advanced packaging have discovered, this can be time-consuming and expensive. It is assumed that once these various approaches can be vetted and standardized, this process will become quicker and cheaper. That could involve sidestepping silicon interposers, which can run as high as $100 for the interposer itself in complex devices that require stitching of multiple reticles.　　“There is overall agreement that silicon interposers are expensive,” said Ram Trichur, director of business development at Brewer Science. “The question is what to replace it with. The challenge with organic interposers has been warpage. There are a lot of companies addressing these challenges and working with certain formats for organic interposers. Some are directly mounted, others need a substrate.”　　Kyocera, Shinko Electronics and Samsung independently have been developing organic interposers using epoxy films that can be built up using standard processes. One of the key issues here has been matching the coefficient of thermal expansion (CTE) with that of silicon. This isn’t a problem with silicon interposers, of course, but it has been an issue with organic laminates and underfill. Reducing the thickness of the interposer layer has been found to help significantly, according to several technical papers on the subject.　　It’s still not clear if this will be a commercially viable alternative to silicon interposers, however. “With an organic interposer you get the same lines and spaces as a silicon interposer, but by the time you address all of the issues you come up with basically the same cost at the end,” said Andy Heinig, a research engineer at Fraunhofer EAS. “The problem is that you need a system-level study to find out which is the best solution for a design. One of the variables is that you need to transfer a huge amount of data on these devices. If you reduce that to a certain point, you can use an organic interposer. But it’s more of a task to find that out than with a silicon interposer.”　　Organic interposers aren’t the only alternative. “There is also work on glass interposers, which are tunable,” said Brewer’s Trichur. “The CTE of glass matches silicon, so you get low loss, which is suitable for high-frequency applications. Glass is also good for panel-level processes, and the cost is low.”　　Interposer alternatives　　One of the big attractions of 2.5D silicon interposers, or “2.1D” organic interposers, is improved throughput using arrays of TSVs rather than skinny wires. That allows a multi-pipe connection to stacks of DRAM, known as high-bandwidth memory.　　The current HBM 2 JEDEC standard, introduced in 2016, supports up to 8 stacked DRAM chips with an optional memory controller, which is similar to the Hybrid Memory Cube. HBM 2 supports transfer rates of up to 2 GT/s, with up to 256 GB/s bandwidth per package. Over the next couple years that will increase again with HBM 3, which will double the bandwidth to 512 GB/s. There is also talk of HBM 3+ and HBM 4, although exact speeds and time frames are not clear at this point.　　The goal of all of these devices is to be able to move more data between processor and memory more quickly, using less power, and 2.5/2.1D are not the only approaches in play at the moment. Numerous industry sources say that some new devices are being developed using pillars—stacked logic/memory/logic—on top of fan-outs. TSMC has been offering this capability for some time with its InFO (Integrated Fan-Out) packaging technology.　　Other high-end fan-outs use a different approach. “Fan-out takes the place of the interposer,” said John Hunt, senior director of engineering atAdvanced Semiconductor Engineering (ASE). “Chip-last is closer to an inorganic interposer, and the yield right now is as high as 99% using 4 metal layers and 2.5 spacing. The real objective of an interposer is to increase the pitch of active devices so you can route HBM2. High-end fan-outs perform better thermally and electrically because the copper RDL is thicker and the vias are less resistive. But they only work in cases where you don’t need 1 micron lines.”　　There are a number of options available with fan-out technology, as well, including chip first, chip last, die up, die down. There also are flip-chip, system-in-package, and fan-out on substrate.　　What’s important is that there are many ways to tackle this problem, and high-speed interconnects are now available using multiple packaging approaches. Until a couple years ago, the primary choices were fan-out, fan-in, 2.5D and 3D-IC and multi-chip modules, and there were distinct performance and cost differences between all of those. There are currently more options on the table for all of those approaches, and the number of options continues to expand, thereby blurring the lines.　　Bridges　　Another approach uses low-cost bridges. Intel has its Embedded Multi-die Interconnect Bridge (EMIB), which it offers to Intel Foundry customers as an option for connecting multiple routing layers.　　Samsung, meanwhile, has announced an RDL bridge for its customers, as well, which accomplishes the same thing inside the redistribution layer (RDL).　　Both of those approaches can certainly cut the cost of advanced packaging, but they are more limited than an interposer. So while a bridge can provide a high-speed connection between two or more chips, there is a limit to how many HBM stacks can be connected to logic using this type of approach.　　Moreover, while the bridges themselves are less expensive than interposers filled with through-silicon vias, they can be challenging to assemble because the connections are planar. The same kinds of warpage issues that affect multi-die packaging apply with bridge technology, as well.　　Future goals and issues　　One of the reasons this kind of in-package, and inter-package interconnect technology is getting so much buzz lately is that the amount of data that needs to be processed is increasing significantly. Some of that must be processed locally, using multiple processors or cores, and some of it needs to be processed remotely, either in a mid-tier server or in the cloud. All of the compute models require massive throughput, and trying to build that throughput into a 7/5nm chip is becoming much more difficult.　　The rule of thumb used to be that on-chip processing is always faster than off-chip processing. But the distance between two chips in a package can be shorter than routing signals from one side of an SoC to another over a skinny wire, which at advanced nodes may encounter RC delay. None of this is simple, however, and it gets worse in new areas such as 5G.　　“There are several materals and process challenges,” said Brewer’s Trichur. “First, you’ve got the structural package issues. Then, when we get into 5G, you’ve got a gap in materials with integrated dielectrics. 5G will be the next materials challenge. So now you’ve got to integrate new materials and new processors, all in a small package. You’ve got more switches, and you also have to integrate antennas, which requires a new process and new materials in itself. This is a whole new challenge.”　　Another market where advanced packaging will play a critical role is in AI/ML/DL. The key metrics there are performance and power, but the bigger challenge is being able to churn out new designs quickly. The problem in this segment is that the training algorithms are in an almost constant state of flux, so being able to add new processors or IP is time-sensitive. An 18-month development cycle will not work if the processor or memory architecture needs to change every six months.　　Trying to utilize off-the-shelf components for a single-chip solution can cause its own set of issues. “One of the problems we’ve been seeing in big SoCs is that companies are trying to glue everything together and the IP models are at different levels of abstractions and different speeds,” said Kurt Shuler, vice president of marketing at ArterisIP. “That requires you to shim and hack the interconnect model to get it to work. Even then, because of the ancestry of the models, they weren’t developed for pins or TCM (tightly coupled memory) interfaces, or they are cycle-accurate or approximately timed or loosely timed. So we’re seeing things that were not developed on a large scale. They were developed as a point problem.”　　Advanced packaging can help that to a point. But most advanced packaging so far has been more about a particular application and a particular project, rather than developing a platform that can be used by many companies.　　“If it works well, you can do great things,” said Raymond Nijssen, vice president of systems engineering at Achronix. “But there are many forks in that road. There are solutions with interposers or without. There are different data rates, so you have some solutions with very high data rates. And if you are doing chiplets, it depends on why you are doing chiplets. Is it because you can’t afford that many balls on a package, or is it an issue of power efficiency because you have a hard ceiling on power usage?”　　Conclusion　　So far, there are no clear answers to any of these questions. But the good news is that there are plenty of options, and many of them have been proven in real products in the market and shown to work.　　The next challenge will be to build economies of scale into the packaging world. That will require the industry to narrow down its choices. Until now, many of these packaging approaches have been expensive to implement, which is why they have shown up in everything from smart phones, where there are sufficient volumes to offset the development cost, or in networking chips, where price is less of an issue.　　In the future, advanced packaging will need to become almost ubiquitous to drive widespread applications of AI/ML/DL inference at edge nodes and in automotive and a variety of other new market segments. That requires repetition with some degree of flexibility on design—basically the equivalent of mass customization. This is the direction the packaging world ultimately will take, but it will require some hard choices about how to get there. The interconnect will remain the centerpiece of all of these decisions, but which interconnect remains to be seen.
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Release time：2018-04-10 00:00 reading：1062 Continue reading>>
PA Semi, Apple ‘<span style='color:red'>Interconnect</span>’ at Startup
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PA Semi, Apple ‘Interconnect’ at Startup

　　With a body of engineering experience at LSI, Cisco, SiByte, Broadcom, PA Semi and Apple, Shailendra Desai is confident of his knowledge in SoC designs and what needs to be done.　　Desai was senior engineering manager at Apple from 2007 to January 2013, where he cut his teeth on issues of interconnect architecture, as well as third-party and in-house IP integration.　　Desai said, “You can license individual IPs from various sources. But none of these IP vendors gave us a platform” to build and connect different IP blocks, in ways that might enable designers to optimize performance per watt for their SoCs. 　　Shailendra Desai　　Desai established Provino Technologies Inc. in 2015 to create a scalable platform for SoCs and IP subsystems. Provino hopes to help designers of SoCs for consumer, automotive and industrial applications where safety, security and energy efficiency are paramount, he explained.　　For consumer products like iPod, iPhone and iPad, for example, it all comes down to how fast and how many derivatives one can pump out based on a single platform, the Provino CEO observed. The same holds true in the IoT SoC market. While acknowledging that IoT is “not a very well-defined space yet,” Desai cited an even greater demand for designing configurable and scalable SoCs quickly — on one platform.　　Early phase　　Provino is still in its early phase. The company has neither talked to the press until now nor explained its technology in depth to industry analysts.　　Provino nonetheless already has one unnamed Japanese automotive customer. Provino currently has 10 large customers evaluating its interconnect platform. “Not a single company has dropped thus far,” said Desai. Provino plans to go for series A funding in the first quarter of 2018.　　The design challenges that Desai encountered with one client, while he was working as a consultant in 2013, foreshadowed similar problems across the board. His client designed an SoC that integrated various cores, including an FPGA. It was built by using Advanced eXtensible Interface (AXI). The company “couldn’t fit their design into an area they had. Meanwhile, AXI was creating a variety of problems such as congestions, latencies and performance,” Desai observed. “When I highlighted such issues in my report, the client said me, ‘Is that it? Can’t you solve the problem for us?’”　　That client became Provino’s first customer. Provino today has 10 people working in California and 15 in India, and it’s hiring.　　Interconnect: ‘Unsung hero’　　During the interview, Desai confessed, “When I started Provino, I had no idea what others were doing” in the interconnect field.　　As Mike Demler, a senior analyst at the Linley Group, put it, “Interconnect IP has been perhaps the unsung hero of the processor industry for at least 20 years. We just don’t hear about it as much as the latest CPU or GPU. ARM, Arteris, NetSpeed, and Sonics have a lot of expertise in this area.”　　Demler explained, “Like any EDA tool and processor IP, there’s always room for improvement. I’d say that the application of machine learning, which NetSpeed is pioneering, could lead to big advances in SoC implementation.” After all, as he concluded, “Hooking up all the components of a billion-transistor chip is an incredibly complex task. Companies that can reduce design time and re-spin costs have an easy value proposition to win over customers.”　　Desai told us that the multiple companies now pursuing the interconnect IP market gives him some comfort. “That means I am in the right market.” Indeed, Desai’s old colleagues at SiByte now hold positions at competing interconnect IP companies such as as Arteris and NetSpeed.　　Building blocks of iFabric　　So, what exactly is Provino’s interconnect platform?　　Desai calls it “iFabric.” The list of iFabric’s building blocks is long, but it boils down to scalable architecture, a foundation for QoS (enabled by virtual channels), multi domain/topology support and integrated safety and security features. 　　iFabric: Scalalbe and configurable architecture (Source: Provino)　　First and foremost, “iFabric is a packetized and serialized bus with a concept of virtual channel,” Desai explained. iFabric provides multiple clocking options from server-class (high-speed) to consumer devices. Support for popular IP interfaces (AXI 3/4, APB and AHB) eases the integration of third-party and in-house IPs, he explained. Stressing its scalable architecture, he noted, “You can add or remove IPs easily so that you can design derivative products quickly.”　　Desai also pointed out that iFabric is built with a foundation for quality of service (QoS). In contrast to other solutions that tend to “suffer from head of line blocking and/or under-utilized resources,” iFabric provides “end-to-end non-blocking QoS,” he claimed. iFabric, designed to support “QoS, traffic shaping and monitoring,” comes with “dynamic arbitration scheme.”　　An important element of iFabric is the concept of virtual channels. Provino noted that virtual channels are key to reducing wires. They provide non-blocking dynamic QoS and help effectively utilize key resources.　　In addition, iFabric offers “physical design” support by providing “placement aware topology, protocol-based reset synchronization and parameterized timing slice insertion.” Speaking of power domain partitioning, Desai said that Provino’s approach enables “partitioning interconnect in optimal way based on topology and physical constraints.”　　Provino’s iFabric offers both PCI and Device Order support, noted Desai. “The world today is in love with ARM. Its Device Order system is not only popular but it’s simpler to use.” In contrast, Intel’s PCIe is “a lot more complex, but when correctly implemented, it offers much higher performance,” he added. “I will not be surprised if PCIe trickles down to consumer systems. That’s why we made our system support both.”　　Given the growing demand for safety and security in automotive and IoT devices, Desai believes iFabric’s integrated features will play an important role. Beyond supporting Trustzone, iFabric offers “tag and memory mapped access control.”　　Inside the iFabric-based SoC, “our customers can use either their own protocols, or Provino’s own link-layer protocol,” according to Desai. Provino’s iLink protocol makes it easy to do pipe insertion between iFabric components, a feature that’s effective when adding features, he explained. Meanwhile, this iLink protocol also allows “centralized access control list for security features tag/ID-based routing,” Desai added, serving as a backbone for safety and security. 　　iFabric Interconnect Platform (Source: Provino)　　Issues and opportunities　　Asked to list issues to be solved by interconnect IP vendors, Richard Wawrzyniak, principal analyst for ASIC & SoC at Semico Research Corp., listed: security in the interconnect network, advanced power management techniques, cache coherency, providing hooks for other type of IP (debug IP, sensors), and extensions to the SoC architecture.　　Wawrzyniak explained, “As device complexity has risen, and the need for complex interconnect IP to tie multiple IP blocks on the SoC together, the interconnect fabric is the ideal place to put robust security functions to ensure the fidelity of the data moving through the architecture.”　　While Provino told EE Times that it provides security functions in its interconnect IP, Wawrzyniak wants more information on what they are. Provino needs to build up these features and make them as robust as possible, he noted.　　During the interview, Provino also said iFabric allows for partitioning the interconnect IP to support multiple clock domains based on topology and physical constraints. Wawrzyniak said this is “a reasonable means of providing power management features, but is not necessarily cutting edge” when compared to what others are doing today.　　Competitions　　Take the example of Sonics, said Wawrzyniak.　　“Sonics has offered advanced power management features as part of their interconnect IP in the form of Energy Processing Units (EPUs) and ICE-grain power architecture fabric, which allow SoC designers to control power consumption right down to the state machine level,” he explained. “In addition, Sonics has also partnered with Moortec to offer connections between Sonics' interconnect IP and Moortec's temperature sensors to enable temperature-compensated, dynamic voltage and frequency scaling (DVFS) in chip designs intended for power-sensitive devices such as mobile/handheld and the Internet of Things (IoT). This is a compelling strategy to allow SoC designers the maximum in flexibility to build in the right level of power management functionality for their silicon solutions.”　　Speaking of other interconnectivity IP vendors who have pioneered the field and worked on cache coherency, the Semico Research analyst noted that Arteris, NetSpeed and Sonics all offer versions of their interconnect IP with features for cache coherency already built in.　　As Wawrzyniak stressed, “One of the biggest benefits to interconnect IP is its ability to evolve and grow over time as the market requirements change. This is not automatic, but must be undertaken and directed by the designers – think one generation of silicon to the next.  All the interconnect IP vendors have this as a main tenet of their approach to the market.”　　Naturally, Provino emphasizes its mission to offer solid QoS features to the designer, using a platform approach. The startup also talks about making room for customization by its customers. But, this is an area that’s difficult to properly quantify, Wawrzyniak added, “since all the interconnect IP vendors would say the same thing.”　　Varying needs for interconnect　　In sum, interconnect issues for SoCs designs are broad and deep. The Linley Group’s Demler said, SoC designers’ challenges differ, “depending on the processor application as well as the particular subsystem within an SoC.”　　Issues such as timing closure are universal, with no single set of requirements for interconnect use in modern processors, Demler explained. “Complex processors integrate a hierarchy of interconnects. That’s why you’ll find so many different interconnects in ARM’s CoreLink family.”　　He said, “For a server processor, the primary issues might be cache coherence, bandwidth, and multicore capacity. For an automotive processor, you’ll have multiple interconnects within heterogeneous subsystems, and you need to address ISO 26262/ASIL requirements for redundancy. Mobile processors in battery-operated devices require cache coherence, I/O coherence, and integration with power management. An IoT processor also needs power management and security is a high priority.”　　In short, “designers are challenged to integrate all of the subsystems in an SoC, so interconnect vendors must include tools to automate synthesis, timing closure, and verification.”　　This explains why the industry might see more new IP suppliers braving the interconnect market. Dan Dobberpuhl　　As for Provino, Desai knows he has come to the market at the right time with the right technology. He explained that he posed his interconnect concept to Dan Dobberpuhl, founder of SiByte and PA Semi more than a few years ago. Citing a long working relationship with Dobberpuhl, Desai said, “We are lucky to get his encouragement, and have him as the chairman of Provino.” Others, said Desai, who have helped Provino include Amrjit Gill, founder of SiByte, PA Semi, Agnilux and Maginatics, and Mark Hayter, a renowned system/SoC architect and engineering director of Google’s Chrome Hardware.
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Release time：2017-11-17 00:00 reading：1595 Continue reading>>
IBM: Copper <span style='color:red'>Interconnect</span>s Here to Stay
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IBM: Copper Interconnects Here to Stay

　　When aluminum interconnects became too slow for complementary metal oxide semiconductors (CMOS) at the 180 nanometer node, IBM led the way to the now universally used copper interconnects starting in 1997.　　Now, on its 20th anniversary, many other interconnects are being proposed to replace copper, notably graphene. IBM, however, claims that slight tweaks to copper deposition will give it an enduring edge all the way to the end of the road for CMOS.　　Big Blue is touting "copper forever" at the IEEE Nanotechnology Symposium this week in Albany, with more details expected to be revealed at the IEEE International Electronic Devices Meeting (IEDM) in San Francisco.　　"Graphene is not readily manufacturable, and furthermore end-to-end comparisons show graphene does not flow uniformly and can't achieve the low resistances of enhanced copper interconnects," IBM Fellow Dan Edelstein told EE Times in an exclusive preview of his Nanotechnology Symposium talk.　　"Copper with a thin cap of cobalt is better than graphene at carrying current and even at the smallest sizes imaginable copper interconnects are still the best solution, perhaps with cobalt, nickel, ruthenium or another platinum-group noble metals brought in to underlay it," Edelstein said.　　Initial IBM studies showed that copper had 40 percent less resistance than aluminum, resulting in an immediate 15 percent burst in processor speeds. Plus, copper is more durable and 100 times more reliable, according to IBM.　　But the industry in the 1990s expressed two big resistances to the changeover to copper — both surmounted by IBM. The first was the fact that copper "poisons" silicon when it comes into direct contact. That was solved by encasing copper in tantalum-nitride and tantalum in a diffusion barrier all around.　　The second was its deposition method. Aluminum was previously fabricated as interconnects by depositing an even layer on a topping of dielectric with vias down to the silicon, after which it was etched. Since copper had to be encased in the tantalum compound, this substrative method was not possible. Instead, IBM came up with an additive method with the kind of electroplating used for printed-circuit boards (PCBs).　　Electroplating had never before been used on CMOS chips, so stumped the rest of the industry until IBM shared its discovery of it and the encasing process to prevent copper poisoning of the underlying CMOS circuitry. The most complicated part of the process, however, was the dual-damascene process of electroplating inside deep trenches, enabling from seven to 17 (then and today, respectively) metal layers to interconnect the single layer of silicon transistors on typical planar chip. And then there was the "magic."　　"We discovered that copper's 'magic' was that in the process of preparing it, trace impurities vastly improved its reliability," Edelstein told EE Times. "Our electroplated copper had minimal electro-migration [the bane of interconnections in microelectronics] because of these traces of carbon, nitrogen, sulfur, chlorine and phosphorus, all of which were present in as little as 10 parts per million."　　Cyprian Uzoh, the chemist on the team (whose name in his native Nigerian language means “copper”) came up with the electroplated copper "recipe" and said at the time of the impurities that "a little salt and pepper never hurt anybody."　　"I firmly believe that the discovery of the superior, cheaper and easier interconnection of CMOS transistors with copper instead of aluminum resulted from IBM Research's multi-disciplinary expertise across chemistry, electrical engineering and physics," Edelstein told EE Times. "Plus, we built our own PCBs, chips and their packaging, which together gave us the expertise to discover how electroplating copper could replace aluminum. All our competitors sub-contracted many of these steps, putting IBM in the unique position to solve the puzzle."　　The dual damascene process, for instance, essentially added silicon dioxide as insulation between layers while simultaneously permitting the tantalum-coated copper wires to be electroplated into the chips trenches. These techniques depended on multidisciplinary expertise, enabling IBM to produce the first prototypes in 1997 and the first production PowerPC chips in 1998. When compared to the previous generation 300-MHz PowerPCs, the 1998 versions experienced a 33 percent boost in speed attributable to their unique copper interconnect. And putting the rest of the industry on the trail to figure out how IBM was doing it.　　"At first our competitors said that it would only last one generation, but so far it has lasted 12. And we believe that for CMOS it will last forever, except perhaps on the bottom layer next to the advanced node silicon transistors which may require cobalt, nickel, ruthenium or another platinum-group noble metals," Edelstein told EE Times.
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Release time：2017-11-16 00:00 reading：1958 Continue reading>>

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