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SK hynix Reportedly Pulls Forward HBM4E Sample Timeline, Eyeing June–July Shipments to Key Customers

　　Samsung announced the start of HBM4E sampling in late May and later unveiled an HBM5 mock-up for the first time at COMPUTEX 2026. Against this backdrop, rival SK hynix is also stepping up its next-generation HBM push, with South Korean media outlet Newsis reporting that the memory giant has secured positive results in HBM4E development and is nearing sample shipments to key customers.　　Notably, certain analysts cited by the report expect SK hynix to begin HBM4E sample shipments as early as this month, or by July at the latest. The company had previously guided that sampling would start in the second half of the year, suggesting the timeline is now being pulled forward, the report adds.　　As Newsis notes, next-generation HBM is highly customized for customers, and earlier sample shipments enable faster performance validation and optimization—ultimately translating into a strategic edge in securing final mass production orders.　　Beyond sampling timelines, broader supply and pricing dynamics are also shifting, which may give early movers key advantages. According to TrendForce, as the market enters 2Q26, negotiations between buyers and suppliers have shifted toward HBM4 supply agreements for 2027, which is expected to become the market’s mainstream project generation. The shift underscores how both Samsung and SK hynix are accelerating HBM4 and HBM4E development amid tightening market cycles.　　SK hynix HBM4E Specs Under Spotlight　　As highlighted by Newsis, SK hynix’s HBM4E is likely to be used in NVIDIA’s next-generation AI accelerator, Rubin Ultra, set for release next year. In line with this platform upgrade, TrendForce notes that NVIDIA’s Rubin Ultra is expected to further increase HBM capacity per GPU to 384GB.　　Against this backdrop of rising system-level requirements, HBM4E specifications are also being pushed higher across the stack. According to Newsis, SK hynix’s HBM4E core die is expected to adopt a 1c DRAM process node, compared with the 1b node used in HBM4. In addition, The Chosun Daily previously reported that the company is likely to use TSMC’s 3nm process for its HBM4E logic die, aiming to challenge Samsung’s 4nm design.　　On the competitive front, Samsung Electronics completed the world’s first shipment of HBM4E samples in late May, supplying them to NVIDIA, according to Yonhap News.　　Samsung’s HBM4E combines a 1c DRAM core die with a 4nm foundry-based base die, delivering speeds of up to 14Gbps per pin and peaking at 16Gbps, equivalent to a maximum bandwidth of 4TB/s, the report notes.

Key word：

SK hynix

Release time：2026-06-16 10:43 reading：347 Continue reading>>

Trade news

Samsung, NVIDIA Deepen Ties as Talks Reportedly Expand to HBM5 Next Year and Next-Gen Groq Chips

　　Following Jensen Huang’s high-profile meetings with SK hynix during his South Korea visit, Samsung Electronics Vice Chairman Jun Young-hyun met with the NVIDIA CEO on June 8 to discuss potential cooperation in HBM and foundry services. According to The Chosun Daily, Jun said the discussions focused on collaboration in HBM and foundry. He added that the near-term priority is to ensure stable supplies of HBM4 and SOCAMM this year, while the two companies also discussed longer-term collaboration beginning next year, including HBM4E, foundry services, and HBM5.　　Samsung, NVIDIA Expand Foundry Cooperation　　On the foundry front, Samsung Electronics is in discussions with NVIDIA on next-generation chip production using its advanced process technologies, including the Drive AGX Thor autonomous driving chip and the Groq language processing unit (LPU), according to Seoul Economic Daily.　　Jun said Samsung is manufacturing NVIDIA’s autonomous driving and Groq chips using 4nm and 8nm nodes, according to ZDNet. He added that the partnership also extends to next-generation Groq chips.　　As highlighted by Seoul Economic Daily, Samsung currently manufactures the third-generation Groq LPU (LP30) on its 4nm process. Jun’s remarks suggest the company is also in position to produce the next-generation LP40, despite industry expectations that TSMC could secure the order through its advanced packaging strengths.　　Samsung Details Memory Portfolio for NVIDIA　　On the memory front, Samsung Electronics is supplying HBM4 (6th-generation) memory with data transfer speeds exceeding 11.7 Gbps per pin for NVIDIA’s Vera Rubin platform, according to Yonhap News. The company is also providing LPDDR5X-based SOCAMM2 modules for the Vera CPU, as well as its PCIe Gen6-based PM1763 storage solution.　　Yonhap News adds that Samsung’s HBM4E combines DRAM core dies with a proprietary 4nm foundry base die, enabling operating speeds of 14 Gbps per pin and achieving up to 16 Gbps in testing.　　Meanwhile, Vice Chairman Jeon stopped short of confirming whether Samsung Electronics and NVIDIA would sign a long-term memory supply agreement, saying Samsung would do its utmost as a key partner to support NVIDIA’s success, according to Newspim.　　NVIDIA CEO Jensen Huang also discussed the company’s partnership with Samsung during a Q&A session following the NVIDIA Korea AI Ecosystem Reception. According to Dealsite, Huang said NVIDIA and Samsung have long collaborated in the Application-Specific Integrated Circuit (ASIC) sector and are jointly developing new ASIC products. He added that the two companies also share a long history of cooperation in memory technologies.

Key word：

Samsung

Release time：2026-06-10 10:37 reading：508 Continue reading>>

Trade news

Largan Expands CPO Push, Plans September Fiber Array Pilot Line, Eyes 2027 Revenue Contribution

　　Taiwan’s Largan Precision, a key optical lens supplier in Apple’s supply chain, is expanding into CPO. According to Liberty Times, Chairman Adam Lin said after the company’s shareholders’ meeting today that Largan plans to establish an automated pilot production line for its fiber array (FA) products in September and may invite a potential major customer to visit the facility.　　Lin said the company has developed a proprietary technology that enables conventional V-grooves and optical fibers to be assembled into high-precision FA products. He noted that tolerance stack-up between V-grooves and optical fibers has been a key challenge for the industry, often forcing competitors to rely on the highest-precision V-grooves and optical fibers to achieve the required accuracy. Largan, however, can use less-than-perfect components to produce FA products with precision below 0.3 microns, outperforming the industry’s typical range of 0.5 to 0.8 microns, the report highlights.　　Largan made its first appearance at Computex this year, showcasing CPO-related solutions and expanding into optical components such as FAUs (fiber array units) and MLAs (microlens arrays). The move is widely viewed as an important signal that the company is seeking new high-margin growth drivers beyond its core smartphone lens business, as noted by China Times.　　The company’s investment in fiber arrays aligns with growing demand for CPO technologies. TrendForce forecasts that co-packaged optics (CPOs) will steadily increase their share of optical communication modules in AI data centers, with penetration potentially reaching 35% by 2030.　　Largan Sees Multi-Row FAs as Next Growth Driver　　FAUs (fiber array units) combine FAs with components such as microlens arrays (MLAs) and prism microlens arrays (PMLAs). According to Liberty Times, Lin expects single-row products to remain the industry’s primary source of demand through 2028. Over the next three to four years, however, rising computing requirements are expected to drive a gradual shift toward two-row, four-row, and eventually eight-row configurations, the report notes. Lin said this transition would play to Largan’s strengths, citing the company’s multilayer stacking and high-precision technologies as key differentiators.　　Largan Eyes 2027 FA Revenue as Qualification Process Advances　　Looking ahead, Lin said FA products could begin contributing to revenue in 2027 if Largan successfully completes customer qualification, the Liberty Times report notes. However, because the products have yet to enter mass production, the company is not currently able to estimate yields or gross margins. Meanwhile, preparations for low-volume production are expected to take about six months to one year. Lin said the production line will be highly automated to improve process precision and manufacturing capacity while reducing reliance on labor-intensive production.

Key word：

Largan

Release time：2026-06-10 10:29 reading：496 Continue reading>>

Trade news

Apple May Debut M5 Ultra-Powered Mac Studio at WWDC, Boosting Demand for TSMC N3P and SoIC-mH

　　Apple’s annual Worldwide Developers Conference (WWDC) is set to kick off on June 9. According to Commercial Times, beyond updates to Apple Intelligence, Siri, and macOS 27, market attention is focused on whether a next-generation Mac Studio powered by Apple’s M5 Ultra chip will also make an appearance.　　The M5 Ultra is expected to retain Apple’s UltraFusion dual-die architecture, combining two M5 Max dies and delivering interconnect bandwidth of more than 1,000GB/s. Specifications are rumored to include a 36-core CPU, an 84-core GPU, and up to 512GB of unified memory, the report adds.　　Notably, as the report highlights, TSMC’s N3P is expected to serve as the key manufacturing foundation for the M5 Ultra, potentially adding to demand for already tight 3nm capacity.　　TSMC’s SoIC-mH Emerges as Potential M5 Ultra Enabler　　TSMC’s advanced packaging is also expected to play a key role in boosting the performance of the M5 Ultra. According to institutional investors cited by Commercial Times, SoIC-mH could emerge as a core technology platform if Apple adopts a higher-density heterogeneous integration approach alongside its UltraFusion high-speed interconnect architecture.　　As TechNews notes, SoIC-mH uses a molded horizontal packaging architecture and integrates multiple chips directly at the wafer level through no-bump hybrid bonding technology. The approach can increase packaging density, improve signal transmission efficiency, and enhance thermal performance.　　In addition, TechPowerUp notes that TSMC’s SoIC-mH allows Apple to separate the CPU and NPU from the GPU. This enables Apple to scale CPU clusters and GPU dies independently, adding more cores as needed. The approach also gives Apple greater flexibility to expand its product lineup without pushing die sizes close to the 830 mm² reticle limit. According to the report, this can improve yields and reduce defects associated with larger silicon dies.　　Despite these potential advantages, the launch timing of the next-generation Mac Studio remains uncertain. According to Macworld, citing Bloomberg, supply-chain constraints are affecting production of Apple’s next-generation professional Macs and could delay the debut of the M5 Ultra-powered system until October 2026.　　Touchscreen MacBooks Could Create New Opportunities for TSMC　　Meanwhile, macOS 27 is another key focus of this year’s WWDC. Commercial Times notes that Apple is expected to strengthen touch support features, laying the groundwork for future touchscreen MacBooks through the early adoption of on-cell touch panel integration.　　Institutional investors cited by the report say that the shift toward OLED displays and touch-enabled MacBooks is expected to drive demand for upgraded display driver ICs, TDDI chips, and touch controllers, while also benefiting TSMC’s specialty process. The report adds that TSMC has completed reliability certification for its 16nm high-voltage process platform and is set to enter the yield-validation stage in 2026, potentially helping customers develop more competitive OLED display driver ICs.

Key word：

Apple

Release time：2026-06-09 13:50 reading：453 Continue reading>>

Trade news

SK Chair Sees Memory Shortage Through 2030, Eyes Capacity Doubling and Stronger TSMC, Taiwan Ties

　　As next-gen HBM solutions has become a key focus at COMPUTEX amid surging AI demand, SK Group Chairman Chey Tae-won made a brief visit to the SK hynix booth on June 2 and spoke with the media. According to TechNews, Chey expects supply-demand tightness in the memory market to persist through 2030.　　Notably, he also said SK will make full efforts to expand production under tight supply conditions, targeting a doubling of total wafer capacity over the next five years, the report adds.　　Marking his first appearance at COMPUTEX, Chey noted that Taiwan has a highly complete AI supply chain and a strong partner ecosystem. As SK Group continues to expand its AI business, he stressed the need to deepen collaboration with more Taiwanese companies. Beyond TSMC, he said meetings with firms such as Foxconn and Asus are also part of this visit to better understand ongoing cooperation and explore ways to further strengthen partnerships, according to the report.　　SK hynix and TSMC have a long-standing partnership, particularly in logic die integration as custom HBM solutions become an emerging industry trend. As previously reported by The Chosun Daily, SK hynix is expected to adopt a 10nm-class 6th-generation (1c) DRAM process for the core die in its HBM4E, paired with a logic die built on TSMC’s 3nm node. For HBM4 supplied to NVIDIA this year, the company is said to be using a 10nm-class 5th-generation (1b) DRAM core die alongside a logic die based on TSMC’s 12nm process.　　Jensen Huang’s SK hynix Booth Visit Marks Another COMPUTEX Highlight　　It is also wort noting that NVIDIA CEO Jensen Huang also visited the SK hynix booth at COMPUTEX 2026 on June 2, meeting SK Group Chairman Chey Tae-won for the second consecutive day, following a dinner meeting the previous evening. According to Chosun Biz, after his keynote the day before—where he directly identified SK hynix as a supplier of next-generation HBM4—Huang toured the exhibition floor and reviewed the company’s latest memory products.　　During the visit, Huang joined Chey at the SK hynix booth to examine the showcased portfolio, including HBM4E wafers and chipset samples, which entered sampling at the end of last month, the report says. It also marked the first public unveiling of an HBM4E physical mock-up, according to Chosun Biz.

Key word：

SK

Release time：2026-06-03 10:57 reading：525 Continue reading>>

Trade news

Nexperia China Says MOSFET, Logic IC Supply Chains Complete as Independent Operations Largely in Place

　　After last year’s control dispute between Wingtech and Nexperia’s Netherlands headquarters sent shockwaves through the industry, Nexperia China now says it has made significant progress in building independent operations. According to EE Times China, Wingtech Chairwoman Ruby Yang announced on May 29 that Nexperia China has largely completed the setup of its independent operating system.　　Yang revealed that Nexperia China’s core management, R&D, and market teams are now fully based in China. The report notes that the company’s capacity and delivery capabilities have steadily recovered, while it continues to build a “China for China, China for Global” full-stack supply chain across wafer manufacturing, packaging and testing, and quality control.　　The announcement comes as Wingtech faces mounting pressure. According to ESM China, the company said on April 29 that its auditor issued a “disclaimer of opinion” on its 2025 financial report, triggering a delisting risk warning under relevant rules.　　Full-Stack Supply Chains Advance Across Key Product Lines　　In terms of product layout, Nexperia China currently covers three core business lines: MOSFETs, logic ICs, and bipolar transistors, including protection devices. Yang said none of the three previously had a fully domestic, full-stack supply chain. However, according to the report, MOSFET and logic IC products have now established such supply chains.　　The bipolar transistor line is being upgraded to a 12-inch platform and is expected to complete its full-stack domestic supply chain within 2026. Bipolar transistors entered small-batch mass production in March 2026, with capacity for protection devices such as ESD (Electrostatic Discharge) and TVS (Transient Voltage Suppressor) products expected to gradually come online in the second half of 2026, the report notes.　　Under the plan, 19 products are expected to be ready for supply by next month, covering more than 80% of demand, the report adds. Despite the severe supply-chain fallout from last year’s Wingtech-Nexperia control dispute, the report indicates that Nexperia China has maintained large-scale delivery capabilities. Since mid-October 2025, it has shipped more than 11 billion chips to over 800 customers.　　Wingtech Seeks Court Action in Nexperia Control Dispute　　Meanwhile, the battle for control of Nexperia has escalated further. According to South China Morning Post, Wingtech said last week that it had filed a lawsuit in a court in China’s southern Guangdong province against Nexperia and three of its executives. The suit demands the restoration of full corporate control and 8 billion yuan, or US$1.18 billion, in compensation.　　As Bloomberg notes, Wingtech asked the court to order the defendants to stop carrying out or supporting the disputed measures, including by withdrawing legal proceedings in the Netherlands and revoking a Dutch ministerial order issued last September under the Goods Availability Act. If the defendants fail to comply, Wingtech would seek the transfer of Nexperia and related subsidiaries to the company free of charge.

Key word：

Nexperia China

Release time：2026-06-02 10:25 reading：613 Continue reading>>

Trade news

SK hynix Introduces iHBM Solution, Targets HBM5 Adoption with 30% Thermal Resistance Reduction

　　As thermal management emerges as a key challenge for HBM, SK hynix has unveiled its iHBM solution, which integrates cooling elements (ICEs) directly into the HBM package. The company plans to adopt the technology in next-generation products, including HBM5, according to its press release.　　According to SK hynix, unlike conventional HBM designs that dissipate heat through the core die, iHBM integrates cooling elements (ICEs), made of thermally conductive, electrically non-conductive silicon-based materials, directly into the D2D PHY between HBM and GPUs, where heat is most concentrated. The company said the technology reduces thermal resistance by 30% and improves operating stability.　　As highlighted by SK hynix, the iHBM solution adopts a structural approach to thermal management by creating an additional heat dissipation path within the package. It also leverages the company’s wafer-level packaging (WLP) process and proven MR-MUF technology to enable stable high-volume manufacturing.　　In addition, its compatibility with existing System-in-Package (SiP) architectures allows customers to adopt the thermal solution with minimal design modifications, SK hynix adds.　　In terms of future roadmap, SK hynix plans to incorporate the iHBM solution into next-generation HBM products, including HBM5, with the goal of improving the stability and efficiency of HPC systems and AI data centers.　　Another Key Technology beyond Hybrid Bonding　　Alongside SK hynix’s latest iHBM solution, hybrid bonding is widely seen as a key approach to addressing heat dissipation challenges in 20-stack HBM, which, as previously reported by The Elec, are expected to become increasingly difficult.　　As explained in the report, hybrid bonding differs from conventional thermo-compression (TC) bonding, which connects chips through soldered micro-bumps. Instead, it bonds dielectric materials such as silicon dioxide (SiO₂) and copper through an annealing process at temperatures of roughly 200°C to 400°C.　　By heating and gradually cooling copper sealed within dielectric layers, thermal expansion and vertical pressure enable direct copper-to-copper diffusion bonding without reaching copper’s melting point, the report notes, adding this approach helps reduce thermal damage to semiconductor circuits while delivering improved thermal and electrical performance.

Key word：

SK hynix

Release time：2026-05-27 10:42 reading：626 Continue reading>>

Trade news

NVIDIA Reportedly Plans GPU-Direct Storage for Vera Rubin, Raising Expectations for HBF Beyond HBM

　　As AI models continue to scale, HBM may struggle to meet future memory-capacity demands, prompting industry experts to view GPU-driven storage architectures as a potential next frontier. According to The Elec, NVIDIA and Amazon are reportedly advancing storage architectures that allow GPUs to directly control storage devices such as SSDs. NVIDIA is said to plan the introduction of GPU-Initiated Direct Storage Access (GIDS) starting with its Vera Rubin AI platform, a shift that could accelerate the emergence of high-bandwidth flash (HBF), the report notes.　　Citing Song Ki-hwan, a professor in the Department of System Semiconductor Engineering at Yonsei University, the report explains that GIDS goes beyond existing GPU Direct Storage (GDS) architecture. Under GDS, CPUs issue data requests to storage devices before data is transferred to GPUs. GIDS advances this by allowing GPUs to access storage directly, bypassing CPUs and DRAM.　　Both GIDS and GDS aim to overcome data-transfer bottlenecks tied to traditional von Neumann computing architectures. Microsoft and AMD are also said to be exploring similar approaches. The report, citing Song, adds that traditional data-transfer methods are inefficient because CPUs are structurally limited in thread processing, while GPUs can generate tens of thousands of parallel threads. Song also notes that GPU-HBM data transfer already accounts for roughly half of total system power, strengthening the case for HBF architectures that place ultra-fast NAND closer to GPUs to address future AI bottlenecks.　　GIDS Could Accelerate HBF and Expand NAND’s Role in AI Memory　　The emergence of GIDS could allow NAND storage to take on a larger role in AI memory systems while easing pressure on HBM capacity. As the report notes, this shift would require higher-performance NAND flash capable of keeping pace with GPU processing speeds. One proposed approach is high-bandwidth flash (HBF), which stacks NAND flash vertically in a structure similar to HBM and connects it using through-silicon vias (TSVs).　　The report notes that NAND flash offers roughly 30 times higher bit density than DRAM, enabling far greater memory capacity in a similar footprint. According to Song, combining six HBF units with two HBM units could increase GPU memory capacity more than 16 times, from 192GB to 3,120GB, potentially supporting AI models with parameter sizes around 16 times larger than current architectures.　　Still, NAND flash has endurance limits, typically supporting only around 100,000 write-and-erase cycles versus DRAM’s near-unlimited write capability. As a result, HBF is seen as better suited for storing AI model parameters, which remain largely unchanged during inference and function as read-only workloads.　　Meanwhile, memory makers have also been exploring GPU-driven memory architectures. According to an Edaily report last year, sources said Samsung Electronics is actively researching next-generation high-performance Z-NAND. The company is also developing GIDS technology that would allow GPUs to directly access Z-NAND-based storage devices. If implemented, GPUs would be able to access Z-NAND devices without intermediaries, potentially shortening processing times for AI workloads.

Key word：

NVIDIA

Release time：2026-05-20 11:20 reading：1292 Continue reading>>

Trade news

YC Chem Reportedly First to Supply Glass Substrate Photoresists; Customer Eyes Year-End Mass Production

　　South Korea’s YC Chem has reportedly become the first in the industry to supply photoresists for glass substrates. According to The Elec, sources say the company is supplying i-line photoresist, stripper, and developer materials for glass substrates to a customer after receiving a purchase order (PO) following qualification tests.　　As supply of related materials begins to ramp up, commercialization of glass substrates also appears to be drawing closer, the report notes. Current shipments are intended for the customer’s prototype production, with material supply volumes expected to increase gradually as the customer moves toward mass production from the end of this year.　　The company is also seeking additional customers. According to the report, it is currently in discussions with more than three companies regarding the supply of glass substrate materials. With some firms, sample testing is underway for negative photoresists and glass substrate coating materials.　　YC Chem has also supplied prototype coating materials for glass substrates to customers. These materials are intended to minimize cracking and warpage caused by differences in thermal expansion coefficients (CTE) and thermal conductivity between glass and copper. According to the report, the products are currently undergoing qualification testing.　　The report notes that the coating materials are used in embedding-type glass substrates, which integrate circuits and passive components directly within the glass substrate itself.　　Key Requirements for Photoresists in Glass Substrate Manufacturing　　As the report points out, the glass substrate photoresist supplied by YC Chem is based on i-line technology, which uses a 365-nanometer (nm) mercury lamp wavelength in the lithography process. Notably, the report points out that, unlike extreme ultraviolet (EUV) photoresists used in advanced semiconductor manufacturing, glass substrate production places greater emphasis on thicker film thickness and strong etch resistance.　　In particular, the report states that through-glass via (TGV) processes require strong chemical durability and high etch resistance during hole formation and copper plating. As a result, demand is increasing for longer-wavelength lithography materials such as i-line and krypton fluoride (KrF)-based photoresists.　　In South Korea, Samyang NC Chem is also developing photoresist materials for glass substrates. The report adds that the company has supplied samples to more than two customers and is reportedly aiming for mass production next year.　　As major companies accelerate glass substrate development, securing stable material supplies is becoming increasingly important. A January Chosun Biz report said Absolics is diversifying suppliers by adding a domestic partner for glass substrate photoresists, reducing reliance on Japan’s TOK, while also reviewing process dualization for TGV and plating processes through additional collaborators.

Key word：

YC Chem

Release time：2026-05-18 13:05 reading：831 Continue reading>>

Trade news

ARM CEO Says Agentic AI May Drive CPU Core Counts to 512 as GPU-CPU Ratios Become Less Relevant

　　The rise of agentic AI is fueling fresh debate over the future GPU-to-CPU balance in AI systems, with Arm CEO Rene Haas now weighing in on the discussion. According to a transcript published by Investing.com, Haas said that while CPUs may not outnumber GPUs on a chip basis, they could from a core-count perspective.　　Haas noted that overall CPU demand is likely to increase significantly as agentic AI scales, with data centers potentially requiring more than four times today’s CPU capacity. He said this could create a data center CPU market opportunity exceeding US$100 billion by 2030.　　At the same time, Haas emphasized that the industry is seeing not only an explosion in overall CPU demand, but also rapid growth in the number of cores per CPU. According to Haas, many agentic AI workloads involve independent jobs, flows, or batches running on dedicated CPU cores, increasing the need for higher-core-count processors.　　Haas used Blackwell, Rubin, and other large AI accelerators as examples, noting that these chips are already approaching reticle limits, meaning their size is constrained by the maximum area a lithography mask can print. In contrast, he said CPU core counts could still double or even quadruple over the coming years.　　Haas noted that the Arm AGI CPU already features 136 cores, significantly higher than many competing offerings. Looking ahead, he said the industry is likely to move toward 256-core and even 512-core CPU designs. He added that such high-core-count architectures play to Arm’s strengths, as efficiency per core becomes increasingly critical at larger scales.　　Mydrivers notes that AMD and Intel are moving in a similar direction. AMD’s 2nm Zen 6-based EPYC processors are already expected to reach up to 256 cores with SMT multithreading support, while Intel’s all-E-core Xeon processors have reached 288 cores, with the next generation expected to scale to as many as 512 cores.　　Regarding the Arm AGI CPU launched at the company’s Arm Everywhere event last quarter, Haas said customer response has been “very strong.” He added that customer demand across fiscal 2027 and fiscal 2028 has already exceeded US$2 billion, more than double the level projected at launch.

Key word：

ARM

Release time：2026-05-11 13:48 reading：698 Continue reading>>

model	brand	Quote
CDZVT2R20B	ROHM Semiconductor
TL431ACLPR	Texas Instruments
RB751G-40T2R	ROHM Semiconductor
MC33074DR2G	onsemi
BD71847AMWV-E2	ROHM Semiconductor

model	brand	To snap up
BU33JA2MNVX-CTL	ROHM Semiconductor
BP3621	ROHM Semiconductor
STM32F429IGT6	STMicroelectronics
IPZ40N04S5L4R8ATMA1	Infineon Technologies
ESR03EZPJ151	ROHM Semiconductor
TPS63050YFFR	Texas Instruments

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