Microsoft First In-House AI Chip “Maia” Produced by <span style='color:red'>TSMC’s</span> 5nm
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Microsoft First In-House AI Chip “Maia” Produced by TSMC’s 5nm

　　On the 15th, Microsoft introducing its first in-house AI chip, “Maia.” This move signifies the entry of the world’s second-largest cloud service provider (CSP) into the domain of self-developed AI chips. Concurrently, Microsoft introduced the cloud computing processor “Cobalt,” set to be deployed alongside Maia in selected Microsoft data centers early next year. Both cutting-edge chips are produced using TSMC’s advanced 5nm process, as reported by UDN News.　　Amidst the global AI fervor, the trend of CSPs developing their own AI chips has gained momentum. Key players like Amazon, Google, and Meta have already ventured into this territory. Microsoft, positioned as the second-largest CSP globally, joined the league on the 15th, unveiling its inaugural self-developed AI chip, Maia, at the annual Ignite developer conference.　　These AI chips developed by CSPs are not intended for external sale; rather, they are exclusively reserved for in-house use. However, given the commanding presence of the top four CSPs in the global market, a significant business opportunity unfolds. Market analysts anticipate that, with the exception of Google—aligned with Samsung for chip production—other major CSPs will likely turn to TSMC for the production of their AI self-developed chips.　　TSMC maintains its consistent policy of not commenting on specific customer products and order details.　　TSMC’s recent earnings call disclosed that 5nm process shipments constituted 37% of Q3 shipments this year, making the most substantial contribution. Having first 5nm plant mass production in 2020, TSMC has introduced various technologies such as N4, N4P, N4X, and N5A in recent years, continually reinforcing its 5nm family capabilities.　　Maia is tailored for processing extensive language models. According to Microsoft, it initially serves the company’s services such as $30 per month AI assistant, “Copilot,” which offers Azure cloud customers a customizable alternative to Nvidia chips.　　Borkar, Corporate VP, Azure Hardware Systems & Infrastructure at Microsoft, revealed that Microsoft has been testing the Maia chip in Bing search engine and Office AI products. Notably, Microsoft has been relying on Nvidia chips for training GPT models in collaboration with OpenAI, and Maia is currently undergoing testing.　　Gulia, Executive VP of Microsoft Cloud and AI Group, emphasized that starting next year, Microsoft customers using Bing, Microsoft 365, and Azure OpenAI services will witness the performance capabilities of Maia.　　While actively advancing its in-house AI chip development, Microsoft underscores its commitment to offering cloud services to Azure customers utilizing the latest flagship chips from Nvidia and AMD, sustaining existing collaborations.　　Regarding the cloud computing processor Cobalt, adopting the Arm architecture with 128 core chip, it boasts capabilities comparable to Intel and AMD. Developed with chip designs from devices like smartphones for enhanced energy efficiency, Cobalt aims to challenge major cloud competitors, including Amazon.
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Release time：2023-11-17 16:00 reading：1998 Continue reading>>
<span style='color:red'>TSMC’s</span> Capacity and Orders Surge, Is the Semiconductor Industry Bouncing Back?
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TSMC’s Capacity and Orders Surge, Is the Semiconductor Industry Bouncing Back?

　　As reported by China Taiwanese media, there’s a gradual uptick in TSMC’s capacity utilization lately, accompanied by a noticeable surge in orders from TSMC’s clients. Some segments of the market are showing signs of rekindled demand, hinting at a possible upswing in the semiconductor industry. Nevertheless, certain semiconductor manufacturing firms remain cautious in their industry outlook.　　TSMC’s Capacity Utilization Rate on the Rise　　Media’s report indicates that TSMC’s capacity utilization rate has gradually recovered. The 7/6nm utilization, which had dropped to 40% at one point, is now around 60% and could potentially reach 70% by the end of the year. Similarly, the 5/4nm utilization is at 75-80%, and the 3nm capacity, which increases seasonally, is approximately 80%.　　Concurrently, TSMC is experiencing a significant uptick in orders from their clients, including tech giants like Apple, MediaTek, NVIDIA, AMD, Intel, Broadcom, Marvell, and STMicroelectronics. Furthermore, AI chip clients such as AMD’s subsidiary Xilinx, Amazon, Cisco, Google, Microsoft, and Tesla have all accepted TSMC’s plan for a price increase in 2024.　　Taking Tesla as an example, they are building a supercomputer facility in Austin to accelerate the development of their autonomous driving system, expanding the computing power of Dojo. The core D1 of Dojo is produced using TSMC’s 7nm process and advanced packaging technology. Based on this, Tesla is deepening its collaboration with TSMC, and it’s expected that their order volume will increase from around 5,000 pieces this year to 10,000 pieces next year.　　Amid the ongoing AI surge, NVIDIA is actively seeking additional production capacity. On October 19th, NVIDIA’s CEO, Jensen Huang, revealed in an interview that the global demand for AI chips remains robust. He has met with TSMC’s CEO, C.C. Wei, to discuss providing more capacity to serve customers. NVIDIA is in the planning stages for the next generation of chips designed for AI-based infrastructure and has also engaged in discussions with partners such as Quanta and ASUS to strategize collaboration.　　Is the Semiconductor Industry on the Rebound?　　During TSMC’s Q3 earnings call, C.C. Wei pointed out that, in addition to strong AI demand, there’s a rebound in demand for smartphones and personal computers. As for automotive electronics, benefiting from the continued growth of electric vehicles, the demand for next year is expected to be quite robust. Regarding when the semiconductor industry might hit bottom, Wei remarked that there are some early signs appearing in the PC and mobile phone sectors. However, it remains challenging to predict a strong resurgence as customers are still cautiously managing their inventories.　　In response to industry concerns about smartphone growth, TSMC’s CFO, Wendell Huang, noted that smartphone growth is anticipated to remain lower than the company’s future growth rate. High-Performance Computing (HPC) is expected to be the most robust growth segment, making substantial contributions to growth in the coming years.　　On the other hand, other semiconductor foundry companies, such as PSMC, have also shared their perspectives on the fourth quarter and future industry developments. Recently, PSMC’s President, Brian Shieh, pointed out that the supply chain’s inventory seems to have reached a reasonable level, with growing demand for mobile panel driver ICs, surveillance system CIS chips, and visibility extending beyond one quarter. Prices for special memory products have started to show an upward trend. Demand for Power Management ICs (PMIC) also displays signs of recovery, even though the trend isn’t as pronounced as that of driver ICs and CIS chips.　　Regarding UMC, the company is scheduled to hold an earning call on 25th October. In their previous earnings call for the last quarter, UMC mentioned that due to ongoing adjustments in the supply chain’s inventory, the outlook for wafer demand remains uncertain. Although the industry glimpsed a modest recovery in the second quarter, the overall sentiment in the end-market remains subdued, and customers continue to maintain stringent inventory management practices.
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Release time：2023-10-25 11:18 reading：1516 Continue reading>>
<span style='color:red'>TSMC’s</span> 2nd Plant in Japan May Receive Up to 900 Billion JPY Subsidy
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TSMC’s 2nd Plant in Japan May Receive Up to 900 Billion JPY Subsidy

　　TSMC is in the process of constructing a semiconductor factory in Kikuyo-cho, Kumamoto Prefecture, Kyushu, Japan (referred to as Plant 1). Production is expected to commence in December 2024. Besides this facility, TSMC has shown interest in establishing a second plant in Japan (referred to as Plant 2). According to Japanese reports, the government is considering providing TSMC with a substantial subsidy of up to 900 billion Japanese Yen for Plant 2.　　On October 4, during the Public-Private Partnership Forum on Increasing Domestic Investment led by Japanese Prime Minister Fumio Kishida, plans were announced for economic measures to be finalized within October. The Ministry of Economy, Trade, and Industry of Japan (METI) will request a budget of 3.4 trillion Japanese Yen to establish three funds supporting semiconductor production and research and development. These funds are the ” Research and Development Project of the Enhanced Infrastructures for Post-5G Information and Communication Systems,” the “Specified Semiconductor Funding Program,” and the “Ensuring Stable Supply Support Fund.”　　As reported by Asahi Shimbun, sources suggest that the METI deems it necessary to grant 900 billion Japanese Yen in subsidies for TSMC’s proposed Plant 2, nearly 600 billion Japanese Yen for the “Rapidus” national team aiming to produce next-gen semiconductor chips domestically, and 700 billion Japanese Yen for traditional chips like Sony CMOS image sensors.　　The Japanese government will allocate the required funds for these economic measures in the 2023 fiscal year supplementary budget. If the METI’s budget request is approved, the budget for semiconductor-elated activities in the 2023 fiscal year supplementary budget (3.4 trillion Japanese Yen) will be 2.6 times higher than that in the 2022 fiscal year supplementary budget (1.3 trillion Japanese Yen).　　The Kishida administration also announced plans to ease land restrictions for crucial manufacturing facilities such as semiconductor plants during the forum. As early as December, local governments will be able to issue development permits for agricultural land, forests, and other areas.　　Before that, local governments could only grant permits for industries related to food logistics, data centers, and plant facilities. Now, this is being expanded to include vital strategic materials. Furthermore, changing the land category from agricultural land often required approvals from multiple government departments, a process that could take more than a year. In the future, these procedures are expected to be shortened to around four months.
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Release time：2023-10-13 11:03 reading：1536 Continue reading>>
<span style='color:red'>TSMC’s</span> AI Orders Set for a Breakout Year in 2023 – Quanta, Wistron, and More Joining the Ride
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TSMC’s AI Orders Set for a Breakout Year in 2023 – Quanta, Wistron, and More Joining the Ride

　　In the industry buzz, it’s reported that TSMC expects a significant upswing in the proportion of AI orders within its 2024 revenue, driven by the increased demand for wafer starts from its six key AI customer groups in the coming year.　　These six major AI customer groups encompass NVIDIA, AMD, Tesla, Apple, Intel, and international giants with in-house AI chip development, entrusting TSMC for production. The orders in this domain continue to heat up, not only benefiting TSMC but also signaling a robust year ahead for AI server manufacturer like Quanta and Wistron.　　TSMC traditionally refrains from commenting on specific customer details and remained silent on market speculations on the October 10th. Meanwhile, AI server manufacturers, including Quanta and Wistron, hold a positive outlook for the upcoming year, with expectations of a continued upward trend in AI-related business operations.　　As the demand for AI wafer starts from key customers intensifies, market experts are keenly watching TSMC’s investor conference on the October 19th. There is anticipation regarding whether TSMC will revise its previous July forecast by further increasing the Compound Annual Growth Rate (CAGR) of AI-related product revenue for the next five years.　　TSMC categorizes server AI processors as those handling training and inference functions, including CPUs, GPUs, and AI accelerators. This category accounts for approximately 6% of TSMC’s total revenue. During TSMC’s July investor conference, it was projected that the demand for AI-related products would see a nearly 50% Compound Annual Growth Rate (CAGR) increase over the next five years, pushing its revenue share into the low teens range.
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Release time：2023-10-11 13:53 reading：1659 Continue reading>>
<span style='color:red'>TSMC’s</span> 3nm Wins Big Qualcomm 5G Deal, Outshines Samsung, Intel
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TSMC’s 3nm Wins Big Qualcomm 5G Deal, Outshines Samsung, Intel

　　According to a report from Economic Daily, TSMC’s 3-nanometer technology has attracted another heavyweight client. Following Apple and MediaTek, it is rumored that Qualcomm will also commission TSMC to produce its next-generation 5G flagship chip using the 3-nanometer process. The chip is expected to be unveiled in late October, making Qualcomm the third client for TSMC’s 3-nanometer technology.　　In response to these rumors, Qualcomm has not provided any comments, while TSMC has chosen to remain silent. Industry experts speculate that TSMC’s 3-nanometer technology will likely attract additional orders from major players such as NVIDIA and AMD in the future. With various leading-edge fabs continuously seeking TSMC’s services, it appears that TSMC’s 3-nanometer technology remains the top choice for international giants.　　Last year, Qualcomm unveiled its annual 5G flagship chip, the “Snapdragon 8 Gen 2,” manufactured using TSMC’s 4-nanometer process. The previous-generation Snapdragon “8 Gen 1” was produced using Samsung’s 4-nanometer process, but it encountered issues related to heat dissipation. Consequently, Qualcomm released an upgraded version, the “Snapdragon 8+ Gen 1,” using TSMC’s 4-nanometer process.　　Qualcomm has traditionally adopted a multi-supplier strategy for semiconductor manufacturing. It is rumored in the industry that Qualcomm has privately informed its smartphone brand customers about the upcoming next-generation 5G flagship chip, the “Snapdragon 8 Gen 3,” expected to be announced in late October. This chip will be available in two process versions: TSMC’s 4-nanometer (N4P) and 3-nanometer (N3E).
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Release time：2023-09-26 14:52 reading：1647 Continue reading>>
<span style='color:red'>TSMC’s</span> 3nm Capacity Hits 100,000 Wafers Next Year, Driven by New Projects
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TSMC’s 3nm Capacity Hits 100,000 Wafers Next Year, Driven by New Projects

　　According to a report by Money DJ, there’s good news from TSMC regarding its 3nm node. Sources within the supply chain have disclosed that the number of new chip designs using the 3nm process, known as “New Tape-Outs” (NTOs), has surged. It’s confirmed that customers including MediaTek, AMD, NVIDIA, and Qualcomm will follow in Apple’s footsteps for mass adoption of the 3nm process in the next year (2024) and the subsequent year. By the second half of next year, the monthly production capacity for the 3nm family, including N3E, will increase from the current approximately 60,000 wafers to 100,000 wafers.　　According to publicly available information from TSMC, the company began volume production of its first 3nm process node, N3, in the second half of last year. The enhanced version of the 3nm process, N3E, started production in the latter half of this year. There will also be extensions to the 3nm process, including N3P, N3S, and N3X. This year, Apple’s high-end A17 Pro chip for its iPhones was based on the initial N3 process.　　Both TSMC and MediaTek previously announced their collaboration, with MediaTek developing new Dimensity products using TSMC’s 3nm process. The design phase, known as “Tape Out,” has been successfully completed, and mass production is scheduled for next year. Industry reports indicate that aside from Apple and MediaTek, AMD, NVIDIA, and Qualcomm are also confirmed to adopt the N3 family of processes. Intel is also on the list, with mass production planned for the year after next.　　TSMC’s first-generation 3nm process currently has a monthly production capacity of about 60,000 wafers, serving Apple as its primary customer. TSMC has initiated a program known as “Continuous Improvement Plan” (CIP) for the 3nm process, referred to as N3B in the industry. Supply chain sources suggest that N3B’s capacity will be integrated into subsequent extended process nodes, such as N3E, which is expected to attract more customers. It is estimated that the overall 3nm monthly production capacity will reach 100,000 wafers by the second half of next year.
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Release time：2023-09-25 15:48 reading：1654 Continue reading>>
<span style='color:red'>TSMC’s</span> U.S. Factory Plans Small-Scale Trial Line for Q1 2024
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TSMC’s U.S. Factory Plans Small-Scale Trial Line for Q1 2024

　　According to a report by Taiwan’s Money DJ, the production schedule for TSMC’s semiconductor foundry in the United States has been delayed until 2025, raising concerns among observers. However, Chairman Mark Liu, in an interview on the 6th, stated that there has been significant progress over the past five months and expressed confidence in the project’s success. Industry sources have indicated that TSMC’s U.S. facility may alter its ramp-up strategy by first establishing a mini-line for trial production, with the expectation of having it in place by the first quarter of 2024.　　TSMC’s Fab 21 Phase 1 construction began in April 2021, originally slated for early 2024 production. However, challenges such as a shortage of skilled equipment installation personnel, local union protests, and differences in overseas safety regulations have caused delays in equipment installation. This has compelled TSMC to adjust its plans, and the expected production timeline is now set for 2025, representing a one-year delay.　　Industry analysts have noted that the efficiency of equipment entering the facility at TSMC’s U.S. plant in Arizona is only about one-third of that of its Taiwan facilities. Given the current pace of progress, the time required for equipment setup to actual production could be substantial. Therefore, TSMC has decided to change its previous ramp-up strategy and first establish a mini-line with an initial estimated monthly capacity of about 4,000 to 5,000 wafers. This approach aims to ensure some level of production output while mitigating potential contract breach issues arising from delays in production.
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Release time：2023-09-08 17:00 reading：3127 Continue reading>>
<span style='color:red'>TSMC’s</span> Outlook Underscores Foundry Market Challenges
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TSMC’s Outlook Underscores Foundry Market Challenges

　　TSMC’s announcement last week that it expects its quarterly sales to decline precipitously quarter to quarter put the chip foundry market on notice as it begins what is expected to be a challenging year.　　TSMC (Hsinchu, Taiwan) said that it expects sales to decline nearly 14% quarter to quarter to between $7.3 billion and $7.4 billion. It would be the largest quarter-to-quarter sales decline for the world’s leading foundry since 2009.　　The expected shortfall has been largely blamed in weaker-than-expected sales of Apple’s newest iPhones, which features Apple-designed processors built by TSMC. But the weak sales guidance is also indicative of larger challenges facing the foundry industry, according to Bill McClean, a veteran semiconductor analyst and president of market research firm IC Insights.　　“The foundry market is in a difficult position in 2019,” McClean told EE Times in an email exchange. IC Insights said earlier this month that nearly all of the pure-play foundry industry’s growth in 2018 came from Chinese firms. TSMC alone saw its revenue from China increase by 61% last year, according to the firm.　　“Apple represented about 22% of TSMC’s sales last year, and we all know that Apple has backed down its expectations for this year,” McClean said. Apple earlier this month cut its sales forecast for the first time since 2002.　　Much of the growth in foundry business from China came from the cryptocurrency business, a market that has softened considerably amid a plunge in cryptocurrency prices, McClean said.　　According to McClean, the pure-play foundry market also faces technology challenges. “TSMC is the only pure-play foundry offering leading-edge feature-sized technology,” he said. “All of the other pure-play foundries are now labeling themselves as specialty foundries, offering embedded memory, image sensor, SOI, etc. technology at relaxed feature sizes.”　　The result has been a glut in specialty foundry capacity, according to McClean. Both TSMC and Samsung — an integrated device manufacturer that also offers leading-edge foundry capacity — are also players in the specialty foundry market, he said.　　“It is so bad now that most foundries talk about overcapacity at the 28-nm node lasting for a couple of years,” McClean said.　　IC Insights is currently forecasting that the foundry market will grow about 2% in 2019, the same growth rate that the firm has projected for the semiconductor industry as a whole.　　TSMC reported sales of $9.4 billion for the fourth quarter of 2018, up 10.7% compared to the third quarter of 2018 and up 2% compared to the fourth quarter of 2017. TSMC reported that 7-nm revenue was 23% of the company’s fourth-quarter total, while 10 nm accounted for 6% and 16/20 nm accounted for 21%.
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Release time：2019-01-23 00:00 reading：1758 Continue reading>>
<span style='color:red'>TSMC’s</span> Roadmap Full, But Thin
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TSMC’s Roadmap Full, But Thin

Continuing to move fast in multiple directions at once, TSMC announced that it is in volume production with a 7-nm process and will have a version using extreme ultraviolet (EUV) lithography ramping early next year. In addition, it gave its first timeline for a 5-nm node and announced a half-dozen new packaging options.Meanwhile, the foundry is pushing power consumption and leakage down on more mainstream 22-/12-nm nodes, advancing a laundry list of specialty processes and rolling out an alphabet soup of embedded memories. At the same time, it is exploring future transistor structures and materials.Overall, the Taiwanese giant expects to make 12 million wafers this year with R&D and capex spending both on the rise. It has even started production of 16-nm FinFET chips in Nanjing, a big first for China.The only bad news is that the advantages with the new process nodes are getting thinner. The new normal for performance gains and power reductions generally fall in a 10% to 20% range, a reality that makes the new packaging and specialty processes increasingly important.TSMC is in volume production of 7-nm chips today with more than 50 tapeouts expected this year. It’s making CPUs, GPUs, AI accelerators, cryptocurrency mining ASICs, networking, gaming, 5G, and automotive chips.The node delivers 35% more speed or uses 65% less power and sports a 3x gain in routed gate density. By contrast, the N7+ node with EUV will only deliver 20% more density, 10% less power, and apparently no speed gains — and those advances require use of new standard cells.TSMC has validated in silicon what it calls foundation IP for N7+. However, several key blocks will not be ready until late this year or early next year, including 28–112G serdes, embedded FPGAs, HBM2, and DDR5 interfaces.Expect 10% to 20% more effort laying out IP for the EUV process, said Cliff Hou, vice president of R&D for design and technology platforms. “We developed a utility to migrate IP with incremental effort.”Fully certified EDA flows for N7+ will be ready by August. Meanwhile, yields of a test 256-Mbit SRAM at N7+ are as good as yields were for the early 7-nm node, he said.Looking ahead, TSMC aims to start risk production of a 5-nm node in the first half of 2019, focusing on mobile and high-performance computing chips.Compared to the initial 7 nm without EUV, the 5-nm node promises a 1.8x greater density than 7 nm. However, it is only expected to reduce power by up to 20% or raise speeds by about 15%, perhaps 25% using Extremely Low Threshold Voltage (ELTV), details of which TSMC has not yet provided.“Without EUV, they can’t deliver the same scaling advantage as past nodes,” said Mike Demler, an analyst with the Linley Group. “If you look at N7+, they claim an additional 20% scaling over N7. So EUV is required to get closer to traditional Moore’s Law scaling. Their N5–N7 scaling just gets worse.”TSMC clearly has a bead on high-volume manufacturing for EUV early next year. It got systems to sustain production at 250 W for a couple of weeks in April and aims to hit 300 W next year, a power level needed for volume throughput.With average daily power levels at 145 W, the foundry has a ways to go, but “throughput is on track to meet production needs,” said Y.J. Mii, vice president of R&D for technology development.Besides “significant progress on power and throughput,” Mii reported that resist dosage is declining toward the foundry’s 1Q19 production goal, though it’s still about a third too high. The protective pellicle transmits 83% of EUV light and should hit 90% next year.EUV continues to provide much better uniformity of critical dimensions than immersion steppers, said Mii, showing several examples. The foundry expects to use EUV on multiple layers in both N7+ and 5-nm nodes and is aggressively installing NXE3400 systems from ASML.It appears that TSMC’s EUV plan is within six months of the production schedule of Samsung, which has said that it will be in production this year. The South Korean giant plans its own event later this month, where it will provide an update on its progress.The gap is not likely enough to get large-volume customers such as Apple or Qualcomm to switch suppliers. In the long term, a lead of a few months will be insignificant, said G. Dan Hutcheson, chief executive of market watcher VLSI Research.Meanwhile, TSMC’s 5-nm node is still embryonic with a version 0.5 EDA flow targeted for June release and a v0.5 design kit in July. Many IP blocks won’t be validated until next year, including PCIe Gen 4, DDR4, and USB 3.1 interfaces.By the end of 2019, the foundry aims to triple to 1.1 million wafers/year its production on 10-/7-nm nodes. It’s latest fab complex 18 is under construction in Taiwan now and aims to start 5-nm production in 2020.Now that TSMC has established its 2.5-D CoWoS package in GPUs and other processors and its wafer-level fan-out InFO in smartphone chips, it is expanding both offerings and adding others.CoWoS chips will have options for silicon interposers up to twice a reticle’s size, apparently stitched in the field, starting early next year. Versions with 130-micron bump pitch will be qualified this year.The InFO technique is getting four cousins. Info-MS, for memory substrate, packs an SoC and HBM on a 1x reticle substrate with a 2 x 2-micron redistribution layer and will be qualified in September.InFO-oS has a backside RDL pitch better matched to DRAM and is ready now. A multi-stacking option called MUST puts one or two chips on top of another larger one linked through an interposer at the base of the stack.Finally, InFO-AIP stands for antenna-in-package, sporting a 10% smaller form factor and 40% higher gain. It targets designs such as front-end modules for 5G basebands.“InFO is an important platform,” said Jan Vardaman, a veteran packaging analyst and president of TechSearch International.“TSMC’s InFO for baseband/modem package in a PoP with memory is very impressive — lower profile, smaller form factor, and better performance. InFO on Substrate is going to be popular because it’s 2-micron lines and spaces will cover a lot of applications.”But that’s not all. TSMC introduced two wholly new packaging options.A wafer-on-wafer pack (WoW) directly bonds up to three dice. It was released last week, but users need to ensure that their EDA flows support the bonding technique. It will get EMI support in June.Finally, the foundry roughly described something that it called system-on-integrated-chips (SoICs) using less than 10-micron interconnects to link two dice, but details are still sketchy for the technique to be released sometime next year. It targets apps from mobile to high-performance computing and can connect dice made in different nodes, suggesting it may be a form of system-in-package.“It used to be ASE leading the way in packaging, but now I’d say TSMC is,” said one analyst during a break.The motivations are clear. As the advantages of CMOS scaling diminish, packaging helps deliver performance, in part through faster memory access. In the last few years, TSMC, which runs three back-end production lines, won significant business with Apple in part due to InFO and Xilinx and Nvidia in part with CoWoS.The new packages “look like the long-promised alternative to the end of Moore’s Law, but pretty expensive and still with lots of issues,” said Demler of Linley Group.Only about a third of TSMC’s business is at advanced nodes such as 28 nm and beyond. Thus, the foundry discussed advances in a laundry list of specialty processes as well as advances a step or two back from the bleeding edge.For example, it is developing ultra-low-power and ultra-low-leakage versions of its 22-nm planar and 12-nm FinFET nodes. They will compete with FD-SOI processes ramping at Globalfoundries and Samsung.The new 22-nm versions use 28-nm design rules and deliver a 10% optical shrink and speed gain or can reduce power 20%. The process and related IP will be ready by the end of the year with target apps including advanced microcontrollers, IoT, and 5G millimeter-wave chips.The 12-nm versions use FinFETs and more compact cell libraries to deliver about 16% more speed than TSMC’s 16FFC. High-speed serdes are among the few pieces of IP that won’t be ready until next year.In memories, a 40-nm resistive RAM is now ready as an alternative to flash for IoT chips. It adds just two mask layers and sports 10 years of retention and support for 10,000 cycles.A 22-nm embedded MRAM will debut this year that’s faster and has longer retention than flash. It targets automotive, mobile, and high-performance designs with good yields on test chips so far.Separately, TSMC is delivering smaller form factors for MEMS. It expects GaN-on-silicon with 10-V and 650-V driver integration in the fall and 100-V D-HEMT qualified next year for cellular power amps.In addition, the foundry has qualified EDA flows and IP for its 16FFC process for automotive. It plans to have a 7-nm automotive process ready by the end of the year, though full certification will take until 2Q19.As icing on the cake, TSMC announced a milestone in China, sketched out its long-term research, and gave an update on its use of machine learning for process automation.The foundry is now producing 16-nm FinFET chips in its new Nanjing fab several months earlier than planned. The first phase in place includes a spaceship-like cafeteria, tubular office building, and 20,000-wafers/month fab that rivals Apple’s new headquarters in flashy design, though not scale. A second phase eventually will double production.Meanwhile, TSMC researchers are progressing on designs of stacked nanowires as nanosheets for a next-generation transistor suitable for work at 2 nm and beyond. The design sports better electrostatics than FinFETs and can be optimized for power and performance by adjusting device width.The foundry sees germanium as a strong candidate to replace silicon, providing lower power at the same speed. It achieved a record-low contact resistance using the material in a CMOS-compatible dielectric.TSMC is exploring a variety of 2D back-end materials including molybdenum disulfide for their atomically smooth surfaces. They also are examining novel ways to enlarge copper grains to reduce resistance in interconnects. In addition, they are working on a selective dielectric-on-dielectric deposition process to enable self-aligning of copper vias.In memories, they are exploring embedded MRAM for use beyond the 22-nm node, possibly with alternative magnetic structures. For embedded ReRAM beyond 40 nm, high-density crossbars are seen as an energy-efficient approach, especially for AI accelerators.In terms of automation, TSMC is embracing machine learning to systematically analyze its wealth of wafer-processing data. It already tunes process recipes for specific tools and products. It also tracks and classifies process variations in an effort to automate the discovery of whether a problem is in a tool, process, or material.The company has a library of more than 50,000 process recipes and tens of millions of control charts. Just how TSMC is applying machine learning to its automation tasks and with what products was unclear — no doubt, still something of a work in progress, perhaps with some secret sauce.
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Release time：2018-05-03 00:00 reading：1130 Continue reading>>

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AMEYA360 mall (www.ameya360.com) was launched in 2011. Now there are more than 3,500 high-quality suppliers, including 6 million product model data, and more than 1 million component stocks for purchase. Products cover MCU+ memory + power chip +IGBT+MOS tube + op amp + RF Bluetooth + sensor + resistor capacitance inductor + connector and other fields. main business of platform covers spot sales of electronic components, BOM distribution and product supporting materials, providing one-stop purchasing and sales services for our customers.

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