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SK hynix Reportedly Pulls Forward HBM4E Sample Timeline, Eyeing June–July Shipments to Key Customers

　　Samsung announced the start of HBM4E sampling in late May and later unveiled an HBM5 mock-up for the first time at COMPUTEX 2026. Against this backdrop, rival SK hynix is also stepping up its next-generation HBM push, with South Korean media outlet Newsis reporting that the memory giant has secured positive results in HBM4E development and is nearing sample shipments to key customers.　　Notably, certain analysts cited by the report expect SK hynix to begin HBM4E sample shipments as early as this month, or by July at the latest. The company had previously guided that sampling would start in the second half of the year, suggesting the timeline is now being pulled forward, the report adds.　　As Newsis notes, next-generation HBM is highly customized for customers, and earlier sample shipments enable faster performance validation and optimization—ultimately translating into a strategic edge in securing final mass production orders.　　Beyond sampling timelines, broader supply and pricing dynamics are also shifting, which may give early movers key advantages. According to TrendForce, as the market enters 2Q26, negotiations between buyers and suppliers have shifted toward HBM4 supply agreements for 2027, which is expected to become the market’s mainstream project generation. The shift underscores how both Samsung and SK hynix are accelerating HBM4 and HBM4E development amid tightening market cycles.　　SK hynix HBM4E Specs Under Spotlight　　As highlighted by Newsis, SK hynix’s HBM4E is likely to be used in NVIDIA’s next-generation AI accelerator, Rubin Ultra, set for release next year. In line with this platform upgrade, TrendForce notes that NVIDIA’s Rubin Ultra is expected to further increase HBM capacity per GPU to 384GB.　　Against this backdrop of rising system-level requirements, HBM4E specifications are also being pushed higher across the stack. According to Newsis, SK hynix’s HBM4E core die is expected to adopt a 1c DRAM process node, compared with the 1b node used in HBM4. In addition, The Chosun Daily previously reported that the company is likely to use TSMC’s 3nm process for its HBM4E logic die, aiming to challenge Samsung’s 4nm design.　　On the competitive front, Samsung Electronics completed the world’s first shipment of HBM4E samples in late May, supplying them to NVIDIA, according to Yonhap News.　　Samsung’s HBM4E combines a 1c DRAM core die with a 4nm foundry-based base die, delivering speeds of up to 14Gbps per pin and peaking at 16Gbps, equivalent to a maximum bandwidth of 4TB/s, the report notes.

Key word：

SK hynix

Release time：2026-06-16 10:43 reading：328 Continue reading>>

Trade news

Lenovo Reportedly Set for July Price Hikes Across Product Portfolio as Memory Costs Pressure PC Market

　　With memory prices remaining elevated, consumer electronics could be heading for another round of price increases. Chinese media outlet Lanjinger.com, citing sources familiar with the matter, reports that Lenovo plans to raise prices across its product lineup from July, broadly in line with the previous round of increases, after the 618 shopping festival ends.　　Notably, Lanjinger.com highlights this would not be Lenovo’s first price hike this year, pointing to March when the PC maker issued nationwide price adjustment notices and raised retail prices for some models by over RMB 1,000. The report adds it has already urged distributors to lock in inventory and secure current pricing ahead of the upcoming increase, with a formal notice expected to be issued by the end of June.　　The pricing pressure is spreading across the PC industry. Dell, as highlighted by the report, has already raised prices on certain products as well, with server prices increasing 20%–40%. Prices for desktops, notebooks, and workstations are also expected to see further significant hikes by July, the report suggests.　　A separate report from Sina also suggests the sharp rise in costs has put pressure on the entire PC industry, prompting several major vendors to begin raising prices as early as six months ago. Dell, according to Sina, increased prices across its commercial PC portfolio in late 2025, with hikes ranging from 10% to 30%.　　Memory Price Surge Drives PC Cost Pressure　　Surging memory prices have become a key driver behind rising costs for PC brands. Lanjinger.com, citing TrendForce data, reports that cumulative spot price increases for DRAM and NAND flash have exceeded 300%. By May 2026, the average price of PC-grade DDR4 8Gb memory had climbed to US$20, the highest level since TrendForce began tracking the market, according to the report.　　Against this backdrop, Taipei Times, citing TrendForce’s latest forecast, reports that global notebook shipments are now expected to decline 13% YoY in 2026, as soaring memory prices and tight CPU supply weigh on demand in the second half—marking a sharper downturn than the 9.4% drop projected in January.

Key word：

Lenovo

Release time：2026-06-11 10:33 reading：448 Continue reading>>

Trade news

Apple May Debut M5 Ultra-Powered Mac Studio at WWDC, Boosting Demand for TSMC N3P and SoIC-mH

　　Apple’s annual Worldwide Developers Conference (WWDC) is set to kick off on June 9. According to Commercial Times, beyond updates to Apple Intelligence, Siri, and macOS 27, market attention is focused on whether a next-generation Mac Studio powered by Apple’s M5 Ultra chip will also make an appearance.　　The M5 Ultra is expected to retain Apple’s UltraFusion dual-die architecture, combining two M5 Max dies and delivering interconnect bandwidth of more than 1,000GB/s. Specifications are rumored to include a 36-core CPU, an 84-core GPU, and up to 512GB of unified memory, the report adds.　　Notably, as the report highlights, TSMC’s N3P is expected to serve as the key manufacturing foundation for the M5 Ultra, potentially adding to demand for already tight 3nm capacity.　　TSMC’s SoIC-mH Emerges as Potential M5 Ultra Enabler　　TSMC’s advanced packaging is also expected to play a key role in boosting the performance of the M5 Ultra. According to institutional investors cited by Commercial Times, SoIC-mH could emerge as a core technology platform if Apple adopts a higher-density heterogeneous integration approach alongside its UltraFusion high-speed interconnect architecture.　　As TechNews notes, SoIC-mH uses a molded horizontal packaging architecture and integrates multiple chips directly at the wafer level through no-bump hybrid bonding technology. The approach can increase packaging density, improve signal transmission efficiency, and enhance thermal performance.　　In addition, TechPowerUp notes that TSMC’s SoIC-mH allows Apple to separate the CPU and NPU from the GPU. This enables Apple to scale CPU clusters and GPU dies independently, adding more cores as needed. The approach also gives Apple greater flexibility to expand its product lineup without pushing die sizes close to the 830 mm² reticle limit. According to the report, this can improve yields and reduce defects associated with larger silicon dies.　　Despite these potential advantages, the launch timing of the next-generation Mac Studio remains uncertain. According to Macworld, citing Bloomberg, supply-chain constraints are affecting production of Apple’s next-generation professional Macs and could delay the debut of the M5 Ultra-powered system until October 2026.　　Touchscreen MacBooks Could Create New Opportunities for TSMC　　Meanwhile, macOS 27 is another key focus of this year’s WWDC. Commercial Times notes that Apple is expected to strengthen touch support features, laying the groundwork for future touchscreen MacBooks through the early adoption of on-cell touch panel integration.　　Institutional investors cited by the report say that the shift toward OLED displays and touch-enabled MacBooks is expected to drive demand for upgraded display driver ICs, TDDI chips, and touch controllers, while also benefiting TSMC’s specialty process. The report adds that TSMC has completed reliability certification for its 16nm high-voltage process platform and is set to enter the yield-validation stage in 2026, potentially helping customers develop more competitive OLED display driver ICs.

Key word：

Apple

Release time：2026-06-09 13:50 reading：447 Continue reading>>

Trade news

TSMC Rejects High-NA EUV Investment Concerns, Confirms Purchase for R&D Use

　　As Intel advances its High-NA EUV roadmap for its A14 node, market attention has turned to TSMC’s comparatively cautious approach to the cutting-edge lithography tool, which is estimated to cost around US$400 million per system.　　However, at its June 4 shareholder meeting, TSMC Chairman C.C. Wei rejected speculation that the company had opted not to invest in High-NA EUV. According to TechNews, he stressed that TSMC has already purchased the equipment and is actively conducting R&D.　　Wei explained that the main reason the High-NA EUV system has not yet been introduced into mass production is purely cost-related. The company will continue working to improve efficiency and reduce costs, and will move the technology into production once conditions are ready, TechNews reports.　　Interestingly, Wei also added with a touch of humor that TSMC is not only investing in the technology but has already purchased the tools, noting that “it would even be a bit embarrassing to say how many.” As previously reported by Tom’s Hardware, citing Kevin Zhang, senior vice president of business development and global sales and deputy COO at TSMC, TSMC’s upcoming A13 and A12 processes, both targeted for 2029, are not expected to require High-NA EUV lithography tools.　　This contrasts with Intel’s strategy for its 14A node and subsequent generations, which are set to adopt High-NA EUV starting in 2027–2028, according to Tom’s Hardware. Reuters, citing ASML CEO Christophe Fouquet, also reported in May that the semiconductor equipment giant expects to see the first memory and logic products manufactured on High-NA EUV systems within the next few months.　　TSMC Reaffirms Strong Capex Outlook　　Against this backdrop, TSMC reaffirmed its capital expenditure plans to support sustained growth. According to TechNews, when investors asked Chairman C.C. Wei how long the company’s current investment cycle would last and when a potential “plateau period” might emerge, he said TSMC remains highly confident in its multi-year outlook, supported by forecasts from both customers and “customers’ customers,” with the company’s growth trajectory expected to continue upward.　　He noted that, as previously guided at the earnings call, capital expenditure for 2026 is projected to range between US$52 billion and US$56 billion, with an internal bias toward the upper end of US$56 billion, as noted by the report.　　Liberty Times adds that at TSMC’s annual shareholder meeting, C.C. Wei said in his opening remarks that the company achieved record-high revenue and profit last year, delivering strong operational results. He noted that TSMC’s share price has risen by more than 1.5 times over the past year, while cash dividend payouts have increased by over 30%.

Key word：

TSMC

Release time：2026-06-05 10:44 reading：537 Continue reading>>

Trade news

Intel Says 18A May Reach Strong Margins by 2027; Notebook Chips on the Node Mark Fastest Ramp in 5 Years

　　Intel is betting heavily on 18A to support the company’s turnaround plan. According to The Register, Chief Financial Officer David Zinsner said that early last year Intel faced the challenge of trying to improve both performance and yield at the same time. The company later shifted its focus to stabilizing performance first, and with that objective largely achieved, it is now concentrating on improving yield month by month.　　Zinsner said Intel’s goal is to achieve yield levels that support strong margins, adding that the company is currently ahead of schedule to reach that target by the end of 2027, as the report highlights. He added that after Lip-Bu Tan joined the company, Intel began sharing more manufacturing data with its vendors. The increased collaboration helped improve yields and made a dramatic difference.　　Looking beyond 18A, Zinsner also expressed confidence in Intel’s 14A. According to the report, he said the company has adopted a more aggressive approach than it did with 18A, adding that yield and performance metrics are currently ahead of where 18A was at the same stage of development.　　Intel 3 and 18A Supply Set to Rise Amid Strong CPU Demand　　In addition to providing an update on Intel’s manufacturing roadmap, Zinsner highlighted growing supply from Intel 3 and 18A, according to Seeking Alpha. As cited by the report, he said Intel expects a meaningful increase in supply from both Intel 3 and 18A over the coming quarters to meet rising demand. He added that 18A-based notebook processors are ramping quickly and represent the company’s fastest-ramping product launch in at least the past five years.　　The company is also seeing rising CPU demand. According to The Register, Zinsner said it remains difficult to predict the full extent of future growth, but he expects the market to be substantial. He said the key challenge at present is supply, adding that Intel sees sufficient demand in the market and should be able to grow data center revenue meaningfully if it executes successfully on planned supply ramps.

Key word：

Intel

Release time：2026-06-05 10:40 reading：470 Continue reading>>

Trade news

SK Chair Sees Memory Shortage Through 2030, Eyes Capacity Doubling and Stronger TSMC, Taiwan Ties

　　As next-gen HBM solutions has become a key focus at COMPUTEX amid surging AI demand, SK Group Chairman Chey Tae-won made a brief visit to the SK hynix booth on June 2 and spoke with the media. According to TechNews, Chey expects supply-demand tightness in the memory market to persist through 2030.　　Notably, he also said SK will make full efforts to expand production under tight supply conditions, targeting a doubling of total wafer capacity over the next five years, the report adds.　　Marking his first appearance at COMPUTEX, Chey noted that Taiwan has a highly complete AI supply chain and a strong partner ecosystem. As SK Group continues to expand its AI business, he stressed the need to deepen collaboration with more Taiwanese companies. Beyond TSMC, he said meetings with firms such as Foxconn and Asus are also part of this visit to better understand ongoing cooperation and explore ways to further strengthen partnerships, according to the report.　　SK hynix and TSMC have a long-standing partnership, particularly in logic die integration as custom HBM solutions become an emerging industry trend. As previously reported by The Chosun Daily, SK hynix is expected to adopt a 10nm-class 6th-generation (1c) DRAM process for the core die in its HBM4E, paired with a logic die built on TSMC’s 3nm node. For HBM4 supplied to NVIDIA this year, the company is said to be using a 10nm-class 5th-generation (1b) DRAM core die alongside a logic die based on TSMC’s 12nm process.　　Jensen Huang’s SK hynix Booth Visit Marks Another COMPUTEX Highlight　　It is also wort noting that NVIDIA CEO Jensen Huang also visited the SK hynix booth at COMPUTEX 2026 on June 2, meeting SK Group Chairman Chey Tae-won for the second consecutive day, following a dinner meeting the previous evening. According to Chosun Biz, after his keynote the day before—where he directly identified SK hynix as a supplier of next-generation HBM4—Huang toured the exhibition floor and reviewed the company’s latest memory products.　　During the visit, Huang joined Chey at the SK hynix booth to examine the showcased portfolio, including HBM4E wafers and chipset samples, which entered sampling at the end of last month, the report says. It also marked the first public unveiling of an HBM4E physical mock-up, according to Chosun Biz.

Key word：

SK

Release time：2026-06-03 10:57 reading：521 Continue reading>>

Trade news

Japan–U.S. NAND Alliance Steps Up Investment as Kioxia–SanDisk Capex Reportedly Rises 40% YoY

　　As South Korea’s memory giants shift focus toward 1c DRAM capacity expansion amid surging demand, Global Economic, citing German tech outlet ComputerBase, reports that the Kioxia–SanDisk alliance is moving fast to reassert its position in the NAND market, capitalizing on an investment gap as Samsung Electronics and SK hynix divert resources toward HBM.　　According to the reports, the U.S.–Japan NAND consortium is expected to execute total capital expenditure of $4.5 billion (about KRW 6.75 trillion) in the current fiscal year, marking a 41% year-on-year increase.　　Notably, a key focus of the alliance would likely be the 10th-generation NAND. Nikkei previously reported that Kioxia plans to begin mass production at its Kitakami site in Iwate Prefecture in 2026. However, given the jump to a 332-layer architecture—up from 218 layers in its 8th-generation devices—the company is expected to repurpose its newly operational Kitakami K2 facility, which began production in September, to support output, according to Nikkei.　　ComputerBase, cited by Global Economic, attributes the strong NAND demand supporting Kioxia–SanDisk’s investment to a structural shift in AI workloads: As AI moves from the training-heavy infrastructure build-out phase to large-scale inference deployment, demand is rising for high-performance, ultra-high-capacity storage.　　At the same time, storage is accounting for a growing share of hyperscaler data center capex, while SSD capacity per GPU is more than doubling year over year, the report notes. As a result, next-gen AI servers are increasingly being designed with tens of terabytes of storage per GPU, driving a sustained surge in NAND demand, the report adds.　　Fewer Layers, Comparable Density　　ZDNet also reports that in its recent earnings briefing, Kioxia identified the launch of 10th-generation BiCS NAND as a key priority for fiscal 2026 (April 2026–March 2027). The report adds that the company applies its proprietary BiCS (Bit Cost Scalable) architecture to its scaling roadmap, with the 10th-generation device delivering 59% higher storage density per unit area and a 33% improvement in data transfer speed compared with the 218-layer generation.　　According to ComputerBase, Kioxia’s stacking approach enables comparable density with fewer layers, translating into meaningful cost advantages. A lower stack height also simplifies vertical etching, reduces high-cost equipment runtime, and helps mitigate wafer warpage defects.　　Based on 3D NAND density estimates cited by Global Economic from ComputerBase, Kioxia / SanDisk BiCS10 is projected to reach 37.6Gb per square millimeter in QLC configuration, which would surpass Samsung Electronics’ upcoming 430-layer V10 TLC architecture at around 28.0Gb.　　Samsung, SK hynix Hold Back　　However, TrendForce indicates that major NAND Flash suppliers will add virtually no new production capacity in 2026, and it seems that South Korean memory players are taking a different approach with Kioxia and SanDisk.　　As highlighted by Global Economic, Samsung Electronics and SK hynix have both adjusted their 10th-generation NAND ramp-up schedules: Samsung has reportedly pushed back its V10 production timeline from the second half of 2025 to 2026, while SK hynix is targeting early 2027 for full-scale production.　　ZDNet also reports that Samsung Electronics had initially planned to begin mass production of its 430-layer 10th-generation NAND this year, but the timeline has been delayed to at least 2027, citing technical complexity and softer demand conditions. The report adds that Samsung is still reviewing investment timing, with no concrete equipment orders confirmed, and that SK hynix faces a similar situation.　　Global Economic notes that if the U.S.–Japan NAND alliance succeeds in lowering cost per terabyte and accelerating QLC enterprise SSD adoption, demand could shift more rapidly toward AI data center storage. Even so, Samsung and SK hynix remain competitive, supported by stable 9th-generation yields and strong enterprise SSD customer bases, the report adds.

Key word：

Kioxia

Release time：2026-06-01 10:45 reading：472 Continue reading>>

Trade news

Samsung Starts Shipping Industry-First HBM4E Samples 3 Months After HBM4 Ramp; Performance Up 20%+

　　Just months after rolling out HBM4 shipments in early 2026, Samsung has begun providing samples of the industry’s first 12-layer HBM4E to major global partners, according to the company’s latest press release.　　Given that HBM4 shares the same 1c DRAM process and 4nm base die architecture as HBM4E, and is already in mass production, industry observers suggest the newly shipped HBM4E samples are also well positioned to transition into mass production. Samsung adds that it plans to proceed with HBM4E mass production in line with client-specific timelines.　　Meanwhile, Samsung is also expanding mass production and supply of HBM4, which became the world’s first HBM4 to enter mass production and shipment in February. In December last year, Samsung’s HBM4 received top-tier evaluation after demonstrating an industry-leading 11.7Gbps speed in System-in-Package (SiP) testing, the final certification stage, the company adds.　　According to News1, the latest development makes Samsung the first to supply HBM4E. Industry observers cited by the report also noted that starting from HBM4, customer-specific design flexibility and stable large-scale supply capabilities will become even more critical. Against this backdrop, Samsung’s integrated strengths across memory, foundry, and advanced packaging are expected to stand out even more clearly, the report adds.　　HBM4E Upgrade with 20% Performance Boost, 30% Higher Capacity　　In terms of performance, Samsung notes that HBM4E marks a notable upgrade over the previous generation, offering a stable 14Gbps pin speed that can scale up to 16Gbps for more demanding AI workloads. Compared with HBM4, the new memory delivers over 20% higher performance and reaches bandwidth of up to 3.6TB/s per stack, significantly improving compute efficiency for large language models (LLMs) and next-generation AI systems.　　Additionally, Samsung’s 12-layer HBM4E is currently offered in a 48GB capacity, which is more than 30% higher than the previous generation. The company plans to expand the lineup to include 32GB (8-layer) and 64GB (16-layer) variants to better align with diverse customer requirements as well.　　From an efficiency standpoint, Samsung highlights that advanced low-power design techniques and an optimized packaging architecture have improved energy efficiency by 16% while reducing thermal resistance by more than 14% compared with the previous generation.　　HBM4E Progress Among Rivals　　Meanwhile, progress from SK hynix and Micron in HBM4E has come under closer market scrutiny following Samsung’s advances. According to Yonhap News Agency, SK hynix had initially planned to begin HBM4E sample shipments in the second half of this year, but recent reports indicate smoother-than-expected development progress, bringing forward its timeline.　　On the other hand, Micron said its first HBM4E product will follow JEDEC standards, with mass production ramp-up targeted for 2027, according to STOCK Analysis.

Key word：

Samsung

Release time：2026-05-29 10:18 reading：677 Continue reading>>

Trade news

SK hynix Introduces iHBM Solution, Targets HBM5 Adoption with 30% Thermal Resistance Reduction

　　As thermal management emerges as a key challenge for HBM, SK hynix has unveiled its iHBM solution, which integrates cooling elements (ICEs) directly into the HBM package. The company plans to adopt the technology in next-generation products, including HBM5, according to its press release.　　According to SK hynix, unlike conventional HBM designs that dissipate heat through the core die, iHBM integrates cooling elements (ICEs), made of thermally conductive, electrically non-conductive silicon-based materials, directly into the D2D PHY between HBM and GPUs, where heat is most concentrated. The company said the technology reduces thermal resistance by 30% and improves operating stability.　　As highlighted by SK hynix, the iHBM solution adopts a structural approach to thermal management by creating an additional heat dissipation path within the package. It also leverages the company’s wafer-level packaging (WLP) process and proven MR-MUF technology to enable stable high-volume manufacturing.　　In addition, its compatibility with existing System-in-Package (SiP) architectures allows customers to adopt the thermal solution with minimal design modifications, SK hynix adds.　　In terms of future roadmap, SK hynix plans to incorporate the iHBM solution into next-generation HBM products, including HBM5, with the goal of improving the stability and efficiency of HPC systems and AI data centers.　　Another Key Technology beyond Hybrid Bonding　　Alongside SK hynix’s latest iHBM solution, hybrid bonding is widely seen as a key approach to addressing heat dissipation challenges in 20-stack HBM, which, as previously reported by The Elec, are expected to become increasingly difficult.　　As explained in the report, hybrid bonding differs from conventional thermo-compression (TC) bonding, which connects chips through soldered micro-bumps. Instead, it bonds dielectric materials such as silicon dioxide (SiO₂) and copper through an annealing process at temperatures of roughly 200°C to 400°C.　　By heating and gradually cooling copper sealed within dielectric layers, thermal expansion and vertical pressure enable direct copper-to-copper diffusion bonding without reaching copper’s melting point, the report notes, adding this approach helps reduce thermal damage to semiconductor circuits while delivering improved thermal and electrical performance.

Key word：

SK hynix

Release time：2026-05-27 10:42 reading：621 Continue reading>>

Trade news

Micron More Upbeat on Outlook, Reportedly Sets 2027 HBM4E Ramp with TSMC for Standard, Custom Logic Dies

　　Two months after its March earnings call, Micron is turning more upbeat on its outlook, while providing additional details on its custom HBM development progress. At the J.P. Morgan 54th Annual Global Technology, Media and Communications Conference, Micron’s Global Operations EVP Manish Bhatia, via STOCK Analysis transcript, said the company’s first HBM4E will be a JEDEC-standard product, with ramp-up scheduled for 2027.　　While Micron is still using 1-beta DRAM for HBM4, Bhatia said the company is expected to transition to 1-gamma DRAM in the HBM4E era. He also confirmed that the logic dies for both standard and custom HBM4E are expected to be manufactured by TSMC.　　When asked about the margin profile of customized products, Bhatia, according to STOCK Analysis, highlighted that value creation stems from multiple proprietary layers: design innovation, robust core DRAM development, and advanced packaging.　　He emphasized that customization represents the next evolution of this value expansion, and as the value increases, customers are expected to be willing to pay for the added customization.　　Improving Outlook vs. Previous Earnings Call　　According to Bhatia, Micron now expects tight conditions across HBM, DRAM, and NAND to persist well beyond 2026. Thus, he noted that the financial outlook has strengthened since the company’s last earnings call, and it is on track for another substantial record free cash flow in fiscal Q3.　　Notably, Bhatia pointed out that while pricing has largely played out as expected, demand remains very strong. He added that the AI ecosystem is shifting from human interactions to agentic and even machine-to-machine workflows, with these agentic workloads increasingly driving inference demand. As inference takes up a larger share of workloads, memory is increasingly seen as a strategic asset for customers, he said.　　Against this backdrop, Micron said in March that it had secured its first strategic customer agreement—a five-year deal with a large customer. Since then, the company has made meaningful progress on additional SCAs, with other customers also showing strong interest in establishing similar strategic relationships with Micron, including in NAND, Bhatia said.　　India Capacity Reported Booked up　　Amid tight demand, Bhatia also said Micron’s global expansion is accelerating. He noted that its Idaho 1 site is progressing well, with the company pulling forward its wafer output timeline from the second half of 2027 to mid-2027.　　Surging memory demand is also driving ramp-up at Micron’s new semiconductor assembly and test facility in Sanand, Gujarat, which began operations in late February. In a separate report by Business Standard, Micron’s entire memory production capacity in India has been fully booked amid strong demand.　　According to a previous Business Standard report, at full capacity, the facility could account for up to 10% of Micron’s global output, supplying both domestic and international markets.　　Sumit Sadana, executive vice-president and chief business officer at Micron, reportedly told Indian media outlet The Economic Times that the global semiconductor memory shortage triggered by the AI boom is proving far more severe than many companies currently anticipate, with the crunch potentially extending well beyond 2028 despite aggressive capacity expansion across the industry.

Key word：

Micron

Release time：2026-05-25 10:44 reading：570 Continue reading>>

model	brand	Quote
TL431ACLPR	Texas Instruments
RB751G-40T2R	ROHM Semiconductor
CDZVT2R20B	ROHM Semiconductor
MC33074DR2G	onsemi
BD71847AMWV-E2	ROHM Semiconductor

model	brand	To snap up
IPZ40N04S5L4R8ATMA1	Infineon Technologies
TPS63050YFFR	Texas Instruments
BP3621	ROHM Semiconductor
ESR03EZPJ151	ROHM Semiconductor
STM32F429IGT6	STMicroelectronics
BU33JA2MNVX-CTL	ROHM Semiconductor

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