<span style='color:red'>SanDisk</span> Goes Beyond HBF: Patent Bonds Processor onto NAND Tile, with HBM Stacks on Shared Interposer
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SanDisk Goes Beyond HBF: Patent Bonds Processor onto NAND Tile, with HBM Stacks on Shared Interposer

　　While SanDisk is speeding up the development of High Bandwidth Flash (HBF), a next-generation architecture that vertically stacks NAND, the company is also advancing additional memory concepts aimed at addressing structural capacity constraints.　　According to a U.S. patent (US 12,430,274 B2) filed and published by SanDisk earlier, the proposed design integrates a multi-core processor directly onto a CBA (CMOS Bonded to Array) memory tile — which itself combines a large NAND flash array with a CMOS logic layer.　　The integrated stack is then mounted on an interposer, with stacks of HBM semiconductor dies affixed around one or more sides of the combined stack, SanDisk notes.　　Rationale Behind the Design　　The design rationale behind SanDisk’s approach, as noted by Wccftech, is partly driven by the inherent limitations of HBM, particularly its relatively constrained capacity, as well as the challenges that HBF has yet to fully address, including latency, power efficiency, and system-level integration complexity.　　To overcome HBM’s capacity ceiling, SanDisk previously introduced its HBF architecture, which adopts a similar concept to HBM by vertically stacking multiple layers of NAND flash and connecting them via through-silicon vias (TSVs) to form a unified memory stack, according to Wccftech.　　While current HBM solutions typically offer 32–64GB per stack, HBF is designed to scale significantly higher, with reported capacity reaching up to 4TB. According to SanDisk, HBF is capable of closely matching HBM’s bandwidth while delivering 8-16x the capacity of HBM at a similar cost.　　However, despite NAND offering higher capacity at a lower cost, Wccftech also points out that it is positioned further from the compute die, resulting in slower data access compared to DRAM-based architectures. In response, SanDisk’s latest patent, as highlighted by the report, proposes a 3D stacking design in which a NAND flash tile, built using a CBA structure, is positioned beneath a compute tile such as an AI accelerator or GPU.　　Under this configuration, HBM DRAM would still be integrated on the same interposer, but would serve a distinct role within the overall memory-compute hierarchy, according to Wccftech. As highlighted by the report, this architecture allows HBM to handle immediate, high-speed memory operations, while the NAND flash layer within the memory tile is used for read/write-intensive workloads and large-scale data storage.
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Release time：2026-06-23 10:58 reading：152 Continue reading>>
Japan–U.S. NAND Alliance Steps Up Investment as Kioxia–<span style='color:red'>SanDisk</span> Capex Reportedly Rises 40% YoY
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Japan–U.S. NAND Alliance Steps Up Investment as Kioxia–SanDisk Capex Reportedly Rises 40% YoY

　　As South Korea’s memory giants shift focus toward 1c DRAM capacity expansion amid surging demand, Global Economic, citing German tech outlet ComputerBase, reports that the Kioxia–SanDisk alliance is moving fast to reassert its position in the NAND market, capitalizing on an investment gap as Samsung Electronics and SK hynix divert resources toward HBM.　　According to the reports, the U.S.–Japan NAND consortium is expected to execute total capital expenditure of $4.5 billion (about KRW 6.75 trillion) in the current fiscal year, marking a 41% year-on-year increase.　　Notably, a key focus of the alliance would likely be the 10th-generation NAND. Nikkei previously reported that Kioxia plans to begin mass production at its Kitakami site in Iwate Prefecture in 2026. However, given the jump to a 332-layer architecture—up from 218 layers in its 8th-generation devices—the company is expected to repurpose its newly operational Kitakami K2 facility, which began production in September, to support output, according to Nikkei.　　ComputerBase, cited by Global Economic, attributes the strong NAND demand supporting Kioxia–SanDisk’s investment to a structural shift in AI workloads: As AI moves from the training-heavy infrastructure build-out phase to large-scale inference deployment, demand is rising for high-performance, ultra-high-capacity storage.　　At the same time, storage is accounting for a growing share of hyperscaler data center capex, while SSD capacity per GPU is more than doubling year over year, the report notes. As a result, next-gen AI servers are increasingly being designed with tens of terabytes of storage per GPU, driving a sustained surge in NAND demand, the report adds.　　Fewer Layers, Comparable Density　　ZDNet also reports that in its recent earnings briefing, Kioxia identified the launch of 10th-generation BiCS NAND as a key priority for fiscal 2026 (April 2026–March 2027). The report adds that the company applies its proprietary BiCS (Bit Cost Scalable) architecture to its scaling roadmap, with the 10th-generation device delivering 59% higher storage density per unit area and a 33% improvement in data transfer speed compared with the 218-layer generation.　　According to ComputerBase, Kioxia’s stacking approach enables comparable density with fewer layers, translating into meaningful cost advantages. A lower stack height also simplifies vertical etching, reduces high-cost equipment runtime, and helps mitigate wafer warpage defects.　　Based on 3D NAND density estimates cited by Global Economic from ComputerBase, Kioxia / SanDisk BiCS10 is projected to reach 37.6Gb per square millimeter in QLC configuration, which would surpass Samsung Electronics’ upcoming 430-layer V10 TLC architecture at around 28.0Gb.　　Samsung, SK hynix Hold Back　　However, TrendForce indicates that major NAND Flash suppliers will add virtually no new production capacity in 2026, and it seems that South Korean memory players are taking a different approach with Kioxia and SanDisk.　　As highlighted by Global Economic, Samsung Electronics and SK hynix have both adjusted their 10th-generation NAND ramp-up schedules: Samsung has reportedly pushed back its V10 production timeline from the second half of 2025 to 2026, while SK hynix is targeting early 2027 for full-scale production.　　ZDNet also reports that Samsung Electronics had initially planned to begin mass production of its 430-layer 10th-generation NAND this year, but the timeline has been delayed to at least 2027, citing technical complexity and softer demand conditions. The report adds that Samsung is still reviewing investment timing, with no concrete equipment orders confirmed, and that SK hynix faces a similar situation.　　Global Economic notes that if the U.S.–Japan NAND alliance succeeds in lowering cost per terabyte and accelerating QLC enterprise SSD adoption, demand could shift more rapidly toward AI data center storage. Even so, Samsung and SK hynix remain competitive, supported by stable 9th-generation yields and strong enterprise SSD customer bases, the report adds.
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Release time：2026-06-01 10:45 reading：487 Continue reading>>

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