Intel Patent Reveals XBM Matching HBM4 Footprint Without Interposers; Commercialization Seen After 2030

　　As AI chip demand surges, existing high-bandwidth memory (HBM) is facing supply and cost challenges, prompting the search for alternative memory technologies. According to Tom’s Hardware, an Intel patent application published on July 2, 2026 reveals the company’s proposed cross-batch memory (XBM) architecture, designed to ease the packaging and cost bottlenecks of today’s interposer-based HBM. The report states that the design aims to match HBM4’s footprint while replacing conventional DRAM and its ultra-wide interface with back-end-of-line (BEOL) transistors and serial Universal Chiplet Interconnect Express (UCIe) links.

　　As noted by Wccftech, XBM is expected to target commercialization after 2030, in line with ZAM, the memory architecture Intel is co-developing with SoftBank subsidiary SAIMEMORY.

　　XBM Architecture and Advantages

　　The proposed architecture centers on DRAM blocks connected to a UCIe I/O block operating at 32 GT/s, with the I/O routed through the base die. According to Wccftech, each XBM stack provides a die capacity ranging from 0.5GB to 5GB. Each sub-channel consists of 12 data blocks, with up to 96 data blocks in an 8-high XBM stack and 192 in a 16-high stack. These channels operate at 2GHz. The report also notes that XBM can be implemented in multiple package configurations, including Memory-on-Package (MoP), enabling higher bandwidth and capacity in smaller form-factor designs.

　　Notably, the memory die uses 1T1C (one transistor, one capacitor) back-end DRAM, with transistors fabricated in the back-end-of-line (BEOL) metal layers rather than front-end silicon, Wccftech says. According to the report, this significantly improves area efficiency, allowing more space for TSVs (Through-Silicon Via) and enabling higher memory density and bandwidth.

　　Competitive and Ecosystem Challenges

　　The global HBM market is currently dominated by South Korean suppliers. As Global Economic News points out, conventional HBM incurs high manufacturing costs due to the micro-bump processes used to vertically stack DRAM dies, while silicon interposers add significant routing complexity and cost. Intel’s proposed XBM architecture is designed to address these limitations.

　　However, Global Economic News also notes that Intel’s proposal is unlikely to immediately shift the industry’s competitive landscape. SK hynix and Samsung Electronics have spent several years developing cost-saving technologies, including standard chiplets, UCIe, and fan-out packaging, to reduce interposer costs. The report further notes that platform compatibility and software ecosystems remain major barriers to adoption. The global AI accelerator ecosystem, led by NVIDIA, is currently optimized for the existing HBM architecture and wide-bandwidth parallel interfaces, making a transition to alternative memory architectures more challenging.