Ameya360:Micron Pushes DRAM Node for Mobile First
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Ameya360:Micron Pushes DRAM Node for Mobile First

　　Micron Technology has been setting the pace for DRAM advancement of late. Its 1-beta DRAM technology continues the trend, but other major vendors are keeping up, even as it looks like DRAM prices will be lower in 2023.　　The company said at the beginning of November that it was shipping qualification samples of its 1-beta DRAM to select smartphone customers and that it’s ready for mass production. The advanced DRAM technology node, which will be used first on Micron’s low-power double data rate 5X (LPDDR5X) mobile memory that delivers speeds of 8.5 Gb/s, follows the company’s 1-alpha DRAM that began volume shipment in 2021.　　Micron’s 1-Beta LPDDR5X provides 16Gb per die capacity, 35% higher than the prior generation, and a 15% power saving compared to prior generation products. Thy Tran, Micron’s VP of DRAM process integration, said the new node is the result of new processes, materials, and equipment to advance Micron’s memory cell integration so it can shrink the memory cell array, including the application of its second-generation high-K metal gate (HKMG) technology. “We can then aggressively scale both the memory cell array in terms of size and also the rest of the circuitry in the dye to save space.”　　Aside from the performance improvements that will benefit smartphone functions such as camera launch, night mode and portrait mode and shake-free, high-resolution 8K video recording and in-phone video editing, Micron’s LPDDR5 based on its 1-beta DRAM boasts additional energy efficiency by implementing JEDEC’s new enhanced dynamic voltage and frequency scaling extensions core (eDVFSC) techniques. Adding eDVFSC at a doubled frequency tier of up to 3,200 megabits per second provides improved power savings controls to enable more efficient use of power based on end-user patterns.　　These features not only represent a faster smartphone camera but also demonstrate how artificial intelligence and machine learning are transforming smartphones into mobile editing studios, Tran said. “Be it photos, videos, or voice processing, memory is at the heart of everything we do.”　　Jim Handy, principal analyst with Objective Analysis, said what’s notable about Micron’s 1-beta is that it demonstrates Micron is strongly oriented toward pushing the technology forward with its HKMG technology to make DRAM as fast as it needs to go. “That makes for a complicated process.” If Micron were just trying to get the bits as cheap as they could be, it wouldn’t touch HKMG, he said.　　So far, DDR5 DRAM has mostly found its way into PCs, said Handy, and less so data centers. But Micron would like to see that change sooner than later so it can sell DDR5 before prices collapse, especially given the fact it’s been eight years since DDR4 was introduced. He noted that the company’s focus of late has been being more profitable rather than dominating market share.　　Although LPDDR5 will be the first to benefit from the 1-beta DRAM technology, Micron will expand the product portfolio that will be manufactured on this node as 2023 progresses for all segments of the memory market including High Bandwidth Memory (HBM).　　Not to be outdone, Samsung Electronics closed out 2022 by announcing the development of its 16-Gb DDR5 DRAM built using what it said is the industry’s first 12-nm-class process technology. Like Micron, Samsung is matching performance gains with power efficiency – its new DRAM consumes up to 23%  less power than its predecessor. Mass production is set to begin in 2023.
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Release time：2023-01-17 11:45 reading：2229 Continue reading>>
Chip designer Mediatek gets Taiwan <span style='color:red'>nod</span> to export goods to ZTE
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Chip designer Mediatek gets Taiwan nod to export goods to ZTE

Taiwanese chip designer Mediatek Inc has received an export permit from the government to sell components to ZTE Corp, a Chinese telecoms equipment maker subjected to restrictions in the United States.The U.S. government last month banned American firms from selling to ZTE for seven years, saying the company had failed to comply with a settlement related to ZTE shipping U.S.-made goods to Iran in violation of U.S. sanctions.Following the U.S. ban, Taiwan had instructed local firms wanting to ship goods to ZTE to apply for permission.Mediatek confirmed to Reuters on Monday that it had received the export permit last week to ship products to ZTE.An official with Taiwan's Bureau of Foreign Trade said the government had approved a permit for Mediatek, and that it had received applications from "several" other tech firms."We fully understand high-tech factories' characteristic of fast-paced shipments of goods, we won't create obstacles for the pace of their exports," the foreign trade official told Reuters, on condition of anonymity."Taiwan's government has its own control mechanisms, which is independent of the way the U.S. looks at it in a given situation," the official said. "The mechanism will consider America and other advanced countries' controls."He said the permit that Taiwan had issued, or was looking to issue, would give domestic companies permission to proceed with exports to firms on the government's watch list.He did not give names of the other companies that had applied for permission, but said chipmaker Nanya Technology Corp was not one of them.Shipments to ZTE by Nanya Tech will be hurt in the short term given the government's procedure, local media has reported.
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Release time：2018-05-10 00:00 reading：1273 Continue reading>>
EUV Defects Cited in 5-nm Node
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EUV Defects Cited in 5-nm Node

　　SAN JOSE, Calif. — Researchers reported random defects appearing in extreme ultraviolet (EUV) lithography at 5-nm nodes. They are applying an array of techniques to eliminate them but, so far, see no clear solution.　　The news comes as Globalfoundries, Samsung, and TSMC are racing to rev EUV systems up to high availability with 250-W light sources for 7-nm production next year. The defects show that there’s no panacea for the increasing costs and complexity of making semiconductors.　　The latest EUV scanners can print the 20-nm-and-larger critical dimensions that foundries plan at 7 nm, said Greg McIntyre, a patterning expert from the Imec research institute in Belgium. However, their ability to make finer lines and holes is unclear, he said in a talk at the SPIE Advanced Lithography conference here.　　Optimists such as McIntyre believe that a basket of solutions will emerge for the so-called stochastic effects. Some skeptics see the results as one more reason to doubt that the expensive and long-delayed EUV systems will become mainstream tools for chipmakers.　　A retired Intel lithographer predicted that engineers will be able to create 5-nm and even 3-nm devices by using two and three passes with an EUV stepper. But a rising tide of chip defects ultimately will drive engineers to new, fault-tolerant processor architectures such as neural networks, said Yan Borovodsky in a keynote at the event.　　The latest defects are cropping up at critical dimensions around 15 nm needed to make 5-nm chips for foundry processes targeting 2020. EUV maker ASML is preparing a next-generation EUV system for printing finer features, but those systems won’t be available until about 2024, it said at the event last year.　　The random defects take many forms. Some are imperfectly made holes; others are tears in lines or shorts where two lines or two holes meet. Given their tiny dimensions, researchers sometimes spend days just to find them.　　McIntyre outlined the challenges finding and eliminating the errors. For example, some researchers are proposing this week a standard way to measure the roughness of lines, one key to understanding the defects.　　Another issue is that it’s unclear exactly what happens to resist materials when hit with EUV light. “It’s still unknown how many electrons are generated and what kinds of chemistries are created … we’re a little ways from a full understanding of the physics, so we’re doing more experiments,” said McIntyre, noting that researchers have tested as many as 350 combinations of resists and process steps.　　“Manufacturing guys will get beat up incredibly over yield loss … if I was going to be responsible for this, I’d say it’s time to retire,” quipped one veteran lithographer during a Q&A session about the 5-nm defects.　　A Globalfoundries technologist provided a more upbeat but sober assessment in another keynote. “It’s been a lot of hard work, and there’s a lot more hard work to come,” said George Gomba, a vice president of research at GF, recalling a nearly 30-year history of work on EUV.　　Today’s NXE 3400 systems are “not meeting some roadmap conditions we desire, so there is still some uncertainty [at 7 nm]. If we do not make productivity and availability improvements, we may only be able to use EUV for the most aggressive processors.”　　Gomba noted that the random defects at 5 nm include subtle 3D breaks and tears such as notches in lines. He also called for more work on so-called actinic systems that inspect EUV masks before lithographers cover them with protective pellicles.　　“To get full use of EUV, we will need actinic inspection systems [still in development], maybe complementing e-beam mask inspection systems” that are available today.　　In an interview, Borodovsky said that another factor that may be contributing to the 5-nm defects is a lack of homogeneity in the current EUV resist materials. Separately, he said that he supports work on direct e-beam writers because the complex phase-shift masks that EUV uses ultimately will balloon to eight times the price of today’s immersion masks.　　Multibeam, a company formed by Lam Research founder David Lam, recently snagged $35 million in government funding for his e-beam technology. He hopes to have commercial systems in 2.5 years for niche applications, but versions suitable for high-volume manufacturing will take much longer, said Lam.　　By 2024, defects could become so widespread that conventional processors will not be able to be made in leading-edge processes, said Borodovsky. Experimental chips using memory arrays with embedded computing elements could be more fault-tolerant, citingIBM’s True North chip and work by HP Labs with memristors.
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Release time：2018-02-28 00:00 reading：1405 Continue reading>>
Qualcomm gets <span style='color:red'>nod</span> from EC, Korea to buy NXP
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Qualcomm gets nod from EC, Korea to buy NXP

　　While it continues to fight off the unwanted advances of Broadcom, Qualcomm has had approval from the European Commission and the Korea Fair Trade Commission to complete its acquisition of NXP Semiconductors. With eight of nine required approvals, only China has yet to pronounce on the deal.　　Steve Mollenkopf, CEO, Qualcomm　　“We are pleased that both the EC and the Korean Fair Trade Commission have granted authorisation of the NXP acquisition and we are optimistic that China will expeditiously grant its clearance,” said Steve Mollenkopf, pictured, Qualcomm’s CEO. “Acquiring NXP is complementary to Qualcomm’s global portfolio, providing tremendous scale in automotive, IoT, security and networking and will greatly accelerate our ability to execute and create value in new and adjacent opportunities.”　　As part of its agreement with the EC and Korea, Qualcomm has committed to exclude certain near-field communication (NFC) patents from the proposed transaction and to ensure that NXP licenses those patents to third parties. It also committed not to assert the NFC patents it will acquire from NXP and to maintain interoperability between Qualcomm’s baseband chipsets and NXP’s NFC chips and rivals baseband chipsets and NFC chips. The deal also requires Qualcomm to continue to offer a license to MIFARE on similar terms to those offered by NXP.
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Release time：2018-01-19 00:00 reading：1268 Continue reading>>
Samsung Secures IoT Node-to-Cloud
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Samsung Secures IoT Node-to-Cloud

　　Samsung announced a soup-to-nuts security offering for the Internet of Things. It is part of the Korean giant’s ambitions to carve out a business in chips for IoT end nodes and gateways as well as cloud services that include machine learning.　　As the next step in that direction, Samsung will start shipping a suite of secure IoT products in November. They span modules with a hardware root-of-trust to encryption and authentication of over-the-air software updates, applications, and cloud services.　　“We believe that security will become a strong value proposition in this space and it will only get stronger … [overall,] our strategy is that we want to be an IoT company internally and externally,” said James Stansberry, general manager of Samsung’s Artik IoT group.　　For Samsung, IoT represents an opportunity to sell a wide variety of processors, memories, and connectivity chips integrated into modules. It also is part of a move to court developers to write cloud-based apps that could serve everything from Artik IoT customers to Samsung’s own increasingly connected systems that range from smartphones to refrigerators.　　“It’s a multidimensional play involving devices, mobile, and consumer electronics,” said Stansberry, who joined Samsung a year ago after running the IoT group at Silicon Labs.　　On the semiconductor side, Artik spans a range of chips from integrated ARM Cortex-M microcontrollers to eight-core applications processors. Today, most of the chips inside its modules, first launched in mid-2015, are from third parties — but that will change.　　“In the beginning, there was little Samsung content, but we are gradually replacing chips with Samsung silicon,” he said.　　For example, an end-node module announced in May includes a Samsung three-core ARM chip with integrated Wi-Fi. Another Samsung integrated chip for end nodes will ship early next year, followed by a Samsung gateway processor with connectivity chips from a third party.　　Stansberry would not discuss the size of the IoT group’s business. Its use of Samsung chips “is modest at this point, but the objective is to increase it,” initially focusing on local area connectivity sweet spots such as Bluetooth, Wi-Fi, Thread, and zigbee aimed at homes, factories, and commercial buildings.　　Market watcher IC Insights ranked Samsung as fourth in 2016 microcontroller sales behind NXP, Renesas, and Microchip. The Korean giant had estimated MCU revenues of $1.87 billion, down 14% from $2.17 billion in 2015, partly because of weak demand for smartcard MCUs. Today, most of the company’s MCUs that don’t go into smart cards are used in Samsung’s own systems, it said.　　Samung’s secure modules will use a standalone secure element to support key storage for secure boot and other features. They will use a variety of standards for encryption, authorization, and signed apps. The company is also expected to roll out cloud-based machine-learning services before the end of the year.
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Release time：2017-10-19 00:00 reading：1457 Continue reading>>
ByteSnap gets the <span style='color:red'>nod</span> from NXP
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ByteSnap gets the nod from NXP

　　Birmingham based electronics consultancy ByteSnap Design has become the first UK based Approved Engineering Consultant for NXP Semiconductors. According to the company, NXP Approved Engineering Consultants are trusted design contractors, software service providers, and training centres that offer experienced consulting or design services to implement NXP technology solutions.　　“We are delighted to be awarded this recognition of our expertise with NXP devices. NXP have long been the leader in embedded application processors and we are looking forward to using the power of the exciting new devices they are launching,” said ByteSnap director Dunstan Power, pictured.　　“ByteSnap Design, with its extensive experience in electronic board design and microprocessor software development, enables NXP’s customers to rapidly get from concept to end product with an optimised usage of the resources we are integrating in our high-performance application processors.” said Gérard Maniez, director of NXP’s third party technical support network.
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Release time：2017-09-30 00:00 reading：1552 Continue reading>>
Na<span style='color:red'>nod</span>iamonds to prevent fires in lithium batteries
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Nanodiamonds to prevent fires in lithium batteries

　　Nanodiamonds can curtail the electrochemical deposition – called plating – that can lead to hazardous short-circuiting of lithium ion batteries, say researchers at Drexel University, Tsinghua University in Beijing, and Hauzhong University of Science and Technology in Wuhan, China.　　To avoid dendrite formation and minimise the probability of fire, current battery designs include one electrode made of graphite filled with lithium instead of pure lithium. The use of graphite as the host for lithium prevents the formation of dendrites. But lithium intercalated graphite also stores about 10 times less energy than pure lithium.　　"Small primary batteries in watches use lithium anodes, but they are only discharged once,” Professor Yury Gogotsi said. “When you start charging them again and again, dendrites start growing. There may be several safe cycles, but sooner or later a short-circuit will happen. We want to eliminate or, at least, minimise that possibility."　　To make lithium anodes more stable and lithium plating more uniform so that dendrites won't grow, the researchers added nanodiamonds to the electrolyte solution in a battery. Nanodiamonds have been used in the electroplating industry for some time as a way of making metal coatings more uniform. When they are deposited, they naturally slide together to form a smooth surface.　　The researchers found that lithium ions can easily attach to nanodiamonds, so that they plate the electrode in the same orderly manner as the nanodiamond particles to which they're linked. The team reports that mixing nanodiamonds into the electrolyte solution of a lithium ion battery slows dendrite formation to nil through 100 charge-discharge cycles.　　According to the team, the breakthrough means that a great increase in energy storage is possible because dendrite formation can be eliminated in pure lithium electrodes.
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Release time：2017-08-30 00:00 reading：1154 Continue reading>>
Intel Quashes Quark for IoT Nodes
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Intel Quashes Quark for IoT Nodes

　　Intel has apparently ended efforts to drive its x86 architecture into microcontroller-class chips and end nodes on the Internet of Things. Analysts generally applauded the move, although they noted it reflects in part on a market for wearables that has not emerged as fast as predicted.　　Multiple reports said Intel has ended sales of Currie and other IoT boards using its Quark processors. However, the company did not directly respond to questions about Quark, a stripped down x86 chip CEO Brian Krzanich announced in his first keynote at the company’s annual developer conference.　　As recently as last August, Intel presented a paper describing its D2000, a 32-bit x86 processor that consumed as little as 35 milliwatts in active mode. At the time the engineer describing the device at Hot Chips said Intel had plans “to scale [Quark] from MCUs to right below the Atom X1000 for Linux with lots of implementation options in cores and SoCs.”　　At one time, Intel fielded as many as three Quark chips — the SE, D2000 and D1000.  All were spins of the original synthesized Pentium-class core Krzanich announced in 2013 as a 32nm part, one-fifth the size and one-tenth the power of Intel’s Atom core.　　Intel rolled out several IoT boards using Quark chips, including several compatible with Arduino starting in October 2013. An Intel spokesman said the company remains committed to supporting the DIY maker movement.　　“IoT remains an important growth business for Intel and we are committed to IoT market segments that access, analyze and share data. These include retail, industrial, automotive and video, which will drive billions of connected devices,” the spokesman said, suggesting the company will focus on Atom-based gateways as its new low end.
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Release time：2017-08-02 00:00 reading：1366 Continue reading>>
Imec Aims 2-D FETs at Sub-5-nm Node
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Imec Aims 2-D FETs at Sub-5-nm Node

　　Designers can extend Moore's Law scaling beyond the 5-nanometer node by choosing two-dimensional anisotropic (faster with the grain) materials such as monolayers of black phosphorus, according to Imec (Leuven, Belgium). Researchers from the nonprofit semiconductor research institute described their findings at the annual Imec Technology Forum, held in San Francisco on the eve of Semicon West (July 11-13).　　Imec’s demonstration project focused on field-effect transistors for high-performance logic applications as part of its Core CMOS program. Using co-optimization at the material, device, and circuit levels, Imec and its collaborators proved the concept using 2-D monolayers of anisotropic black phosphorus with a smaller effective mass in the transport direction. The black phosphorus was sandwiched between interfacial layers of low-k dielectric, with stacked dual gates deployed atop high-k dielectrics to control the atomically thin channels.　　Imec demonstrated the co-optimization approach at the 10-nm node but says the architecture could function with sub-half volt (<0.5-V) power supplies and an effective oxide thickness of less than 50 angstroms (0.5 nm), allowing its FETs to extend Moore’s Law for high-performance logic applications below the 5-nanometer node.　　The researchers predict the demonstrated architecture, materials, and co-optimization technique will yield reliable FETs with thicknesses all the way down to the single-atom level and gate lengths as short as 20 ?, advancing the nanowire FET as the successor to the FinFET. Imec is evaluating other materials besides black phosphor as prime candidates for extending nanowire FETs to atomic-level 2-D channels.　　Beyond extending Moore’s Law scaling laws for FETs, the 2-D materials will enhance the development of photonics, optoelectronics, biosensing, energy storage, and photovoltaics, according to Imec.　　The institute conducted the research in collaboration with scientists from Belgium’s Catholic University of Leuven (Belgium) and Italy’s Pisa University. Funding for the 10-nm demonstration came from the European Union’s Graphene Flagship research initiative along with Imec’s Core CMOS Program partners, which include GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, and TSMC.　　For more details, see the free Nature scientific report “Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes,” in which Imec presents guidelines on choosing materials, designing the devices, and optimizing the performance of sub-10-nm high-performance logic chips. Imec explains that at gate lengths below 5 nm, the 2-D electrostatistics associated with gate stacking become more of a challenge than direct source-to-drain tunneling for 2-D-material-based FETs.
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Release time：2017-07-14 00:00 reading：1379 Continue reading>>
TSMC Tips 7+, 12, 22nm Nodes
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TSMC Tips 7+, 12, 22nm Nodes

　　Trying to cover the waterfront, TSMC disclosed plans for new high-, mid- and low-end processes at an annual event here. They included an enhanced 7nm FinFET node using extreme ultraviolet lithography, a 12nm upgrade of its 16nm process and a 22nm planar technology — its answer to fully depleted silicon-on-insulator (FD-SOI).　　The foundry also described enhancements to its two chip-stacking techniques, advances in RF CMOS and work in transistors and materials, paving the way to a 3nm node and beyond. In addition, it previewed design capabilities using machine learning that it will offer before the end of the year.　　Among its achievements, TSMC noted 76 percent yields on the 256Mbit SRAM made in its first-generation 7nm node, which will be in volume production next year. It also reported that an ARM Cortex-A72 processor in the node exceeded 4GHz using a new design flow.　　The proliferation of different nodes, sub-nodes and platforms threatens to create a dizzying array of options. TSMC has clearly focused on easing migrations for designers, sometimes at the expense of advances measured in single digits.　　The Taiwan company, already the world’s largest foundry by far, expects to ship 11 million 12-inch-equivalent wafers this year, a typical 10 percent annual increase. The biggest share—two million wafers—will use its planar 28nm processes for which it is boosting capacity 15 percent this year.　　TSMC has taped out nearly 800 chips using flavors of its 28nm process. It has shipped 4.5 million 28nm wafers to date, clearly a big sweet spot it aims to defend.　　Globalfoundries hopes to capture many of those customers starting this year with 22nm FD-SOI, a lower cost, lower power alternative with similar performance to TSMC’s 16nm FinFET node. TSMC claims its 22nm process provides an easier migration path from 28nm while FD-SOI requires redesigned intellectual property cores.　　“Bulk semiconductor technology has been enhanced for 30 years and is used by Intel and Samsung,” the world’s two largest chip makers, said Mark Liu, TSMC’s co-chief executive in a brief interview after a keynote here. “FD-SOI will always be the technology of the future,” he quipped.　　The news comes the same day NXP announced it will use FD-SOI for multiple future processors. So far, a total of just 10,000 FD-SOI wafers/month are shipping from all fabs including Globalfoundries and STMicroelectronics, said Sam Wang, a chip analyst for Gartner.　　Globalfoundries may be slightly ahead in timing, ramping its 22nm FD-SOI process now with Sony image sensors in production. TSMC said its 22nm process will be in production next year, aimed at 5G RF and other mobile chips including image processors and components for wearables and the Internet of Things.　　The 22nm FD-SOI node sports similar specs to TSMC’s 22nm process, “but it does not have the comprehensive IP ecosystem… and the manufacturing track record we have,” said B.J. Woo, vice president of business development at TSMC.　　TSMC also plans an ultra-low power version of its 12nm FinFET process, supporting 0.5V operation and starting risk production before June. It will likely be positioned as a competitor to the 12nm FD-SOI process Globalfoundries announced last year but is not expected in production until 2019.　　The ultra-low power TSMC 22nm process should deliver a 20 percent area shrink and either 0.45x the power or 1.32x the speed of its 28 HPM process, Woo said. Compared to its 28 HPC+ process, the 22nm is a direct optical shrink with better transistors and 0.6 Vdd operation offering 10 percent smaller size and 35 percent less power or 15 percent more speed, she said.　　TSMC’s 22nm node uses the same mask counts, design rules, SRAM bit cells and I/O devices as its 28HPC+ node. Designers only need to adopt its boosted transistors and re-characterize foundation IP to ensure they meet new margins, Woo said.　　“The migration effort is really different [from FD-SOI]—it’s a day and night difference,” said Jack Sun, a vice president of R&D at TSMC.　　TSMC’s Liu said the foundry expects 70 tape outs of IoT chips this year across its family of ultra-low power processes that range from 55 to 28nm. The 40nm ULP process has been characterized for near-threshold operation driving energy efficiency to 11 microamps/MHz, he said.
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Release time：2017-03-14 00:00 reading：5555 Continue reading>>

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