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GigaDevice's Dual-Power Supply SPI NOR Flash for 1.2V <span style='color:red'>SoCs</span> Halves Read Power Consumption

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GigaDevice's Dual-Power Supply SPI NOR Flash for 1.2V SoCs Halves Read Power Consumption

　　GigaDevice, a leading semiconductor company specializing in flash Memory, 32-bit microcontrollers (MCUs), sensors, analog products and solutions, has unveiled the GD25NE series of dual-power supply SPI NOR Flash, designed specifically for 1.2 V system-on-chip (SoC) applications.　　The GD25NE series strengthens GigaDevice's strategic dual-power supply Flash roadmap, providing seamless compatibility with next-generation 1.2 V SoCs and eliminating the need for an external booster circuit. With its higher performance and lower power consumption, the GD25NE series addresses the growing demand for advanced embedded storage, making it an ideal choice for wearable devices, healthcare, IoT, data center and Edge AI applications.　　Combining a 1.8 V core voltage with a 1.2 V I/O interface voltage, GD25NE supports single, dual, quad STR (single transfer rate) and quad DTR (double transfer rate) operation. It achieves high-speed clock frequencies of up to 133 MHz in STR mode and 104 MHz in DTR mode.　　With a typical page program time of 0.15ms and sector erase time of 30ms, the GD25NE series significantly outperforms conventional 1.2 V-only Flash solutions—offering up to 20% faster read performance, over 60% faster program speed, and 30% reduction in erase time. Due to these advances, it makes the GD25NE series an outstanding choice for emerging embedded applications.　　The GD25NE series is engineered with ultra-low power consumption by design, making it ideal for energy-sensitive applications. It features a typical deep power-down current of just 0.2 µA, a Quad I/O DTR read current of 9mA at 104 MHz, and program/erase currents as low as 8 mA. Compared to conventional 1.8 V solutions, the 1.2 V design reduces power consumption by up to 50%. This optimized power architecture not only enhances power efficiency but also simplifies system design while maintaining higher performance.　　“The GD25NE series represents a new class of dual-supply SPI NOR Flash, delivering an optimal balance of high performance and ultra-low power consumption," said Ruwei Su, GigaDevice vice president and general manager of Flash BU, "With significantly reduced power usage, faster read speeds, and enhanced program/erase efficiency, this solution is designed to meet the evolving demands of next-generation 1.2 V SoCs. As part of our ongoing commitment to innovation, we continue to expand our portfolio, providing customers with more efficient, reliable, and future-ready Flash solutions for new leading-edge applications”

Key word：

GigaDevice

Release time：2025-03-12 10:59 reading：485 Continue reading>>

ROHM’s PMICs for <span style='color:red'>SoCs</span> have been Adopted in Reference Designs for Telechips’ Next-Generation Cockpits

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ROHM’s PMICs for SoCs have been Adopted in Reference Designs for Telechips’ Next-Generation Cockpits

　　ROHM has announced the adoption of its PMICs in power reference designs focused on the next-generation cockpit SoCs ‘Dolphin3’ (REF67003) and ‘Dolphin5’ (REF67005) by Telechips, a major fabless semiconductor manufacturer for automotive applications headquartered in Pangyo, South Korea. Intended for use inside the cockpits of European automakers, these designs are scheduled for mass production in 2025.　　ROHM and Telechips have been engaged in technical exchanges since 2021, fostering a close collaborative relationship from the early stages of SoC chip design. As a first step in achieving this goal, ROHM’s power supply solutions have been integrated into Telechips’ power supply reference designs. These solutions support diverse model development by combining sub-PMICs and DrMOS with the main PMIC for SoCs.　　For infotainment applications, the Dolphin3 application processor (AP) power reference design includes the BD96801Qxx-C main PMIC for SoCs. Similarly, the Dolphin5 AP power reference design developed for next-generation digital cockpits combines the BD96805Qxx-C and BD96811Fxx-C main PMICs for SoC with the BD96806Qxx-C sub-PMIC for SoC, improving overall system efficiency and reliability.　　Modern cockpits are equipped with multiple displays, such as instrument clusters and infotainment systems, with each automotive application becoming increasingly multifunctional. As the processing power required for automotive SoCs increases, power ICs like PMICs must be able to support high currents while maintaining high efficiency. At the same time, manufacturers require flexible solutions that can accommodate different vehicle types and model variations with minimal circuit modifications. ROHM SoC PMICs address these challenges with high efficiency operation and internal memory (One Time Programmable ROM) that allows for custom output voltage settings and sequence control, enabling compatibility with large currents when paired with a sub-PMIC or DrMOS.　　Moonsoo Kim,　　Senior Vice President and Head of System Semiconductor R&D Center, Telechips Inc.“Telechips offers reference designs and core technologies centered around automotive SoCs for next-generation ADAS and cockpit applications. We are pleased to have developed a power reference design that supports the advanced features and larger displays found in next-generation cockpits by utilizing power solutions from ROHM, a global semiconductor manufacturer. Leveraging ROHM’s power supply solutions allows these reference designs to achieve advanced functionality while maintaining low power consumption. ROHM power solutions are highly scalable, so we look forward to future model expansions and continued collaboration.”　　Sumihiro Takashima,　　Corporate Officer and Director of the LSI Business Unit, ROHM Co., Ltd.“We are pleased that our power reference designs have been adopted by Telechips, a company with a strong track record in automotive SoCs. As ADAS continues to evolve and cockpits become more multifunctional, power supply ICs must handle larger currents while minimizing current consumption. ROHM SoC PMICs meet the high current demands of next-generation cockpits by adding a DrMOS or sub-PMIC in the stage after the main PMIC. This setup achieves high efficiency operation that contributes to lower power consumption. Going forward, ROHM will continue our partnership with Telechips to deepen our understanding of next-generation cockpits and ADAS, driving further evolution in the automotive sector through rapid product development.”　　・ Telechips SoC [Dolphin Series]　　The Dolphin series consists of automotive SoCs tailored to In-Vehicle Infotainment (IVI), Advanced Driver Assistance Systems (ADAS), and Autonomous Driving (AD) applications. Dolphin3 supports up to four displays and eight in-vehicle cameras, while Dolphin5 enables up to five displays and eight cameras, making highly suited as SoCs for increasingly multifunctional next-generation cockpits. Telechips is focused on expanding the Dolphin series of APs (Application Processors) for car infotainment, with models like Dolphin+, Dolphin3, and Dolphin5, by leveraging its globally recognized technical expertise cultivated over many years.　　・ ROHM 's Reference Design Page　　Details of ROHM’s reference designs and information on equipped products are available on ROHM’s website, along with reference boards. Please contact a sales representative or visit ROHM’s website for more information.　　https://www.rohm.com/contactus　　■ Power Supply Reference Design [REF67003] (equipped with Dolphin3)　　Reference Board No. REF67003-EVK-001　　https://www.rohm.com/reference-designs/ref67003　　■ Power Supply Reference Design [REF67005] (equipped with Dolphin5)　　Reference Board No. REF67005-EVK-001　　https://www.rohm.com/reference-designs/ref67005　　About Telechips Inc.Telechips is a fabless company specialized in designing system semiconductors that serve as the “brains” of automotive electronic components. The South Korean firm offers reliable, high-performance automotive SoCs. In response to the industry’s transition toward SDVs (Software Defined Vehicles), Telechips is broadening its core portfolio beyond car infotainment application processors (APs) to include MCUs, ADAS, network solutions, and AI accelerators.　　As a global, comprehensive automotive semiconductor manufacturer, Telechips adheres to international standards such as ISO 26262, TISAX, and ASPICE, leveraging both hardware and software expertise for future mobility ecosystems, including not only automotive smart cockpits, but also E/E architectures. What’s more, Telechips provides optimal solutions for In-Vehicle Infotainment systems (IVI), digital clusters, and ADAS, all compliant with key automotive standards (AEC-Q100, ISO 26262). Telechips has established business relationships with major automakers both domestically and internationally, supported by a strong track record of shipments.　　One flagship product is the Dolphin5 automotive SoC that integrates an Arm®-based CPU, GPU, and NPU to meet high-performance requirements. As a fabless company, Telechips outsources the manufacturing of its SoCs to Samsung Electronics’ foundry, delivering high-quality semiconductor products to domestic and overseas manufacturers. For more information, please visit Telechips’ website:　　https://www.telechips.com/　　*Arm® is a trademark or registered trademark of Arm Limited.　　TerminologyPMIC (Power Management IC)　　An IC that contains multiple power supply systems and functions for power management and sequence control on a single chip. It is becoming more commonplace in applications with multiple power supply systems in both the automotive and consumer sectors by significantly reducing space and development load vs conventional circuit configurations using individual components (i.e. DC-DC converter ICs, LDOs, discretes).　　SoC (System-on-a-Chip)　　A type of integrated circuit that incorporates a CPU (Central Processing Unit), memory, interface, and other elements on a single substrate. Widely used in automotive, consumer, and industrial applications due to its high processing capacity, power efficiency, and space savings.　　AP (Application Processor)　　Responsible for processing applications and software in devices such as smartphones, tablets, and automotive infotainment systems. It includes components such as a CPU, GPU, and memory controller to efficiently run the Operating System (OS), process multimedia, and render graphics.　　DrMOS (Doctor MOS)　　A module that integrates a MOSFET and gate driver IC. The simple configuration is expected to reduce design person-hours along with mounting area and to achieve efficient power conversion. At the same time, the built-in gate driver ensures high reliability by stabilizing MOSFET drive.

Key word：

ROHM

Release time：2024-12-20 13:56 reading：750 Continue reading>>

GigaDevice Introduces 1.2V SPI NOR Flash Product to Meet Advanced <span style='color:red'>SoCs</span>' Need for ultra-Low Power and High Performance

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GigaDevice Introduces 1.2V SPI NOR Flash Product to Meet Advanced SoCs' Need for ultra-Low Power and High Performance

　　GD25UF series featuring single 1.2V supply offers industry's lowest Active Read power consumption　　GD25UF's 1.2V capability enables a direct interface to SoCs and processors produced on advanced process nodes, reducing their die size and simplifying their power supply architecture　　Nuremberg, Germany – 14 March 2023 – GigaDevice, a semiconductor industry leader in Flash memory and 32-bit microcontrollers serving a broad range of technology innovations, today introduced the GD25UF series of SPI NOR Flash in its strategic roadmap of 1.2V Flash products supporting systems-on-chip (SoCs) and applications processors built on advanced process nodes. The GD25UF SPI NOR Flash products are optimized for applications that require ultra-low power consumption or a small board footprint.　　The GD25UF products operate at a supply-voltage range of 1.14V-1.26V .This is ideal for devices built on advanced process nodes and operating at a core voltage of 1.2V, as it provides for a simpler power system architecture, and for direct interfacing between the I/O pins of the SoC or processor and the GD25UF device.　　With the GD25UF products, GigaDevice provides better specifications than other competing 1.2V products in the parameters that manufacturers of mobile communications devices, wireless modems and wearable devices care most about. In low-power mode at a frequency of up to 50MHz, Active Read current can be as low as 0.4mA at slower frequencies. Deep power-down current of 0.1µA makes the GD25UF ideal for any battery-powered or wearable application. In addition, industry-best program and erase times help increase device manufacturing throughput while reducing system power consumption.　　In Fast Read mode, these Flash devices operate at up to 120MHz and achieve a data-transfer rate of up to 640Mbits/s. In low EMI mode, operating at 80MHz over a double transfer-rate (DTR) quad I/O interface, the GD25UF products achieve the same data-transfer rate of 640Mbits/s while minimizing clock-generated noise, an ideal feature for noise-sensitive wireless applications.　　The 64Mbit GD25UF64E is in production now. It is supplied in SOP8, 3mm x 4mm or 4mm x 4mm USON8 and WLCSP packages, or as a known good die. The 128Mbit GD25UF128E is sampling. Products with memory capacity of 32Mbits and 256Mbits are in development.　　Syed S. Hussain, Flash BU Global Segment Marketing of GigaDevice said: 'Users of chips manufactured at advanced process nodes require a new generation of low-voltage Flash memory products that are optimized for the demanding applications that they support, such as IoT devices, mobile phones, PCs and laptops, and consumer devices, e.g. portable healthcare, smart watch and battery-based devices. Today’s launch of the GD25UF64E 1.2V Flash product marks the start of a comprehensive roadmap of low-voltage Flash products from GigaDevice, providing OEMs with the mix of memory capacities, serial interfaces and security functions that they need for the next generation of system designs. There is a Megatrend, where one shrinks SoCs down to lowest process geometry a must requirement is peripherals needs to support 1.2VIO also. GigaDevice is uniquely positioned to win Ultra-low power and performance megatrend in new designs.'　　GigaDevice will be exhibiting its portfolio of Flash memory and microcontroller products at Embedded World　　Come and visit GigaDevice in person or through LIVESTREAM:　　GigaDevice Booth Hall 3A – 527: Embedded World, March 14 – 16, 2023, Exhibition Center Nuremberg, Germany.　　Conference Presentations:　　Performance, Efficiency and Reliability: GigaDevice's Arm® Cortex®-M33-based MCU Family.　　GigaDevice Flash Journey in Automotive: Flashes Low Voltage Mega-Trend

Key word：

GigaDevice

Release time：2023-11-01 16:22 reading：1919 Continue reading>>

Ameya360:How to Select Wireless <span style='color:red'>SoCs</span> for Your IoT Designs

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Ameya360:How to Select Wireless SoCs for Your IoT Designs

　　Selecting a wireless system-on-chip (SoC) for your design isn’t easy. It requires careful consideration around several factors, including power consumption, size and cost. The SoC also needs to support the right wireless protocols for the IoT application and network, which then entails factors like range, latency and throughput.　　Max Palumbo, product marketing manager for wireless connectivity, secure connected edge, at NXP Semiconductors.　　One way to ensure that your IoT design is optimized for the application is by carefully considering your choice of wireless SoCs. It also requires a careful evaluation of the key requirements of your design—including battery life, compute and memory resources, and footprint—because there will be performance tradeoffs, depending on the application.　　Designers have many factors to consider when selecting wireless SoCs for their products, said Max Palumbo, product marketing manager for wireless connectivity, secure connected edge, at NXP Semiconductors. “There is no right answer in terms of what device or architecture to choose, as this depends on the series of engineering tradeoffs that the product designer is willing to make to satisfy the needs of their end customer.”　　There is also industry agreement that a strong development ecosystem with comprehensive support tools and service is paramount. These product and prototyping tools and services can help designers reduce their time to market and cost.　　So let’s address some of the top-of-mind design issues that engineers should consider when selecting wireless SoCs for their IoT designs, as well as some of the biggest challenges and tradeoffs.　　Use cases dictate design　　Most wireless SoC manufacturers agree that the application requirements determine the selection of the wireless SoC and help narrow down the options for the IoT design. One of the most critical factors is power consumption, they said, followed by a host of other considerations, such as wireless protocols, performance, cost, size, tool support and ease of integration.　　While power consumption is tapped as one of the most critical factors in selecting wireless SoCs, choice of the wireless protocol is governed by the application.　　The end application determines the priorities, said Brandon Bae, senior director of product marketing for wireless connectivity at Synaptics Incorporated.　　He cited a few application examples in which design priorities define the selection of the wireless SoC.　　“For example, if it’s a battery-powered device, such as a wearable with a single Bluetooth connection, they may choose our SYN20703P [single-chip Bluetooth transceiver and baseband processor],” Bae explained. “If it’s a drone, they may need our SYN43400 Wi-Fi SoC, as power consumption and size—and weight—are very important and developers have to make the decision based on their go-to-market strategy.　　“A drone may also need both Wi-Fi and Bluetooth,” he added. “At that point, the number of wireless interfaces required for the application becomes important, and an integrated SoC with both is typically the best approach. Our SYN43756 [single-chip IEEE 802.11ax 2 × 2 MAC/baseband/radio with integrated Bluetooth 5.2] is a good solution for that.”　　Bae also noted that “application dependency can be extrapolated to include aggregation points or gateways for the IoT where multiple heterogeneous wireless networks come together.” This would benefit from a higher level of integration, with Bluetooth, Wi-Fi and Zigbee/Thread (IEEE 802.15.4 PHY), such as that provided by the Triple Combo SYN4381 wireless SoC, he said.　　Dhiraj Sogani, senior director of wireless product marketing at Silicon Labs, agreed: “Every wireless protocol is playing a different role, and the end-application use cases are the most important in deciding one or more of these protocols for an IoT device.”　　Sogani said there are several key factors in selecting a wireless SoC for an IoT device, which vary by the application. His top five considerations, which are important for all kinds of IoT devices, include wireless protocols; security; battery life; hardware and software support, including peripherals, GPIOs, IDE support, cloud support and networking/wireless stack integration; and compute and memory resources available for the application after the OS, networking stacks and the wireless stacks have been integrated into the wireless SoC.　　For wireless protocols, requirements include application throughput, latency, number of network nodes and range, he said. “IoT devices are becoming more complicated every day as more functionality is getting integrated into the devices. Adding wireless to the IoT devices increases the complexity manifold. There are many wireless protocols being used in IoT devices, including Wi-Fi, BT, BLE, Zigbee, Thread, Z-Wave and cellular. The choice of wireless communication protocols for a particular device depends upon the application, size, cost, power and several other factors.”　　Sogani cited several examples in which the application, together with the performance requirements, are key to the decision-making.　　“BLE is a good protocol to use for a home-temperature sensor, as it consumes low power, it is lower in cost than some other protocols and it provides the necessary range in a typical home environment,” he said. “NFC provides the lowest throughput and the shortest range, making it ideal for contactless-payment–like applications. Wi-Fi provides higher application throughput needed for several applications, such as security cameras.”　　Design challenges　　Most chipmakers agree that wireless SoCs can simplify designs by integrating the different wireless protocols and handling the coexistence challenges between multiple protocols. They also deliver space savings, a key concern in many IoT designs. However, there are use cases where discrete solutions could offer the best value in terms of both performance and cost.　　“The benefits of a wireless SoC are many and include the assurance of a proven design, shorter time to market, smaller overall footprint, lower bill of materials [BOM] and lower inventory management costs,” said Synaptics’ Bae. “These advantages apply to mostly all end applications, but there may be instances where a discrete solution may work better if the customer has specific requirements and has the RF design skills and resources to implement in that direction.”　　NXP’s Palumbo said that when determining how to architect an end product that includes wireless connectivity, “one of the first decisions a product designer must make is whether they will use a single, integrated wireless SoC or separate the wireless from the processor. An equally important decision that needs to be made is which operating system will be used. The decision of the operating system will quickly shift designers either to lower-cost, RTOS-based microcontrollers or toward larger, more scalable, Linux-based processors.”　　Integrated wireless SoCs are physically smaller and may be lower-cost due to the integration, enabling the end-product designer to deliver a smaller product or a more innovative form factor, said Palumbo.　　“However, the challenge with an integrated wireless SoC is that the designer lacks flexibility to optimize the compute performance or the wireless performance independently and the capabilities of the wireless SoC itself are invariant, so there is not as much ability to optimize individual components of the product,” he said.　　Whether using an integrated or discrete solution, power consumption is still a key factor that is influenced by the system architecture and use cases. “This means in some cases, multi-chip solutions involving separate radio and processor chips may be easier to optimize,” said Palumbo. “In other cases, wireless processors may provide all the necessary flexibility needed for specific applications and use cases.”　　Palumbo provided some key examples in which power consumption plays a critical role. “For example, simple end applications like a sensor or actuator that have a low communications duty cycle and do not perform any ancillary networking functionality, such as routing, designers will see the lowest power consumption when using an integrated wireless SoC.” This type of application can be addressed with devices like NXP’s K32W148 wireless microcontroller.　　“However, for more complex devices—a thermostat, for example—where packet routing is an important feature for the overall user experience of the end device and the target ecosystem, a discrete solution may be lower power,” he said. “If a network co-processor [NCP] is included alongside the primary compute SoC, then this allows the networking stacks to be offloaded so that only the co-processor itself is required to wake up to route packets.”　　In this example, an NXP i.MX microprocessor like the i.MX 8M Mini can be used as the compute SoC, the NXP RW612 wireless MCU can be used as an NCP and the IW612 tri-radio solution can be used as a radio co-processor. “This can help reduce the power consumption of the system significantly—especially when an NCP is used with a Linux-based microprocessor as the primary compute platform,” said Palumbo.　　The product designer has to analyze these tradeoffs and select the architecture that makes the most sense for the value they are trying to bring to their customers, he added.　　Design tradeoffs　　Wireless integration can be quite challenging especially as it relates to RF circuitry, according to manufacturers of wireless SoCs, and all tradeoffs are driven by the use cases.　　The challenge is often about the radio-integration part of the solution to deliver good-quality product performance and to meet regulatory and protocol certification requirements, said Nathalie Vallespin, wireless product line marketing manager at STMicroelectronics.　　Nathalie Vallespin, wireless product line marketing manager, STMicroelectronics.　　“A wireless SoC simplifies the integration phase, as most customers first moving to wireless solutions are not RF experts, so integration simplifies and accelerates their development and production,” she said. “Product sourcing for end customers is also simplified by an integrated solution [SoC] and can be even further simplified using a module, which includes the whole reference design.”　　In addition, Vallespin said that “an SoC also ensures more efficient power and performance levels of the radio protocol and application, while a multi-chip solution creates connection interface constraints and complexity for software management. A discrete/multi-chip approach can also potentially lead to overconsumption to keep both host and radio running to communicate properly.”　　Synaptics’ Bae said there are many challenges with RF, but “they can be addressed through careful consideration of board layout, grounding, relative positioning of other digital ICs in the design to avoid interference, and antenna placement and routing. Aside from layout, the designers or developers need to be cognizant of the impact on the SoC from power-source switching, other sources of electromagnetic interference and materials choice for enclosures.”　　Wireless SoC integration can become challenging, depending on the number of wireless protocols it supports and the use cases, said Silicon Labs’ Sogani.　　He cited several challenges, including hardware integration (antenna placement, RF design, etc.), software development (wireless stacks, networking stacks, cloud connectivity, application development), RF testing (including extreme conditions), interoperability testing (with other devices it is supposed to connect to), wireless coexistence (multiple protocols need to co-exist), production testing (minimizing the test time and yield), regulatory certifications (for countries to be supported), protocol compliance (for protocols integrated in the device), power optimization (based on the battery requirements), system security (to ensure device and data security) and solution cost (based on the target).　　Designers need to make a tradeoff at every step to optimize between various parameters, and all of these tradeoffs are eventually drive by the application use cases, said Sogani.　　“With IoT devices needing to support multiple protocols, wireless SoCs provide an integrated solution that simplifies designs by integrating these protocols and handling the coexistence challenges between multiple protocols on the same ISM band internally, as well as not having to worry about managing and worrying about RF design for multiple devices,” he added. “This helps in faster development cycles and more seamless functionality between the various protocols. End applications do play a role, as it may be possible to use discrete chips for simpler applications, but as applications become complicated, it makes more sense to use integrated solutions.”　　Vallespin said understanding and selecting the right technology that will be the best fit for the application and market demand is a key challenge. Another challenge is understanding the chosen radio protocols and picking the right hardware (antenna, routing, BOM selection) and matching software, which can be specific to each technology, she said.　　The key tradeoffs are balancing price versus features as well as choosing the architecture—a host + co-processor approach or a single application processor, Vallespin added.　　Support and availability　　In addition to performance concerns, development and design support along with supply-chain issues like continued availability are priorities for many IoT designers.　　Key concerns include how effectively the product and its development ecosystem can reduce their time to market and cost, the availability of the product and prototyping tools and the long-term availability of the product, said Vallespin.　　There are also several questions that designers need to ask, such as if there are guarantees that the SoC will be available as long as their product is in the market, what the roadmap of the SoC is and if it aligns with their product development plan, and if there is sufficient support availability, including for documentation, ecosystem and contact to ensure success, she added.　　NXP’s Palumbo believes longevity requirements are part of the tradeoff equation.　　“Once a product has shipped, the hardware itself is unchanging; however, there is an expectation from the end customer that the product will continue to be supported and receive updates for some time after their purchase,” said Palumbo. “Selecting a device—and a product architecture—that enables product designers to provide updates for the lifetime of the product is a criterion that is gaining importance.”　　The software architecture is also another critical consideration when selecting a wireless SoC, said Palumbo. “Regardless of the product architecture—be it integrated wireless SoC or discrete—the software tools and environment for these SoCs are equally important components to the hardware. Whether a device is Linux-based, Android-based, or RTOS-based—even without considering the wrinkle of which RTOS to use from the myriad of solutions available—makes a massive impact on the end product.”

Key word：

Wireless,SoC,IoT

Release time：2023-02-24 15:30 reading：1809 Continue reading>>

Ameya360:Wireless <span style='color:red'>SoCs</span> Solve Connectivity Challenges

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Ameya360:Wireless SoCs Solve Connectivity Challenges

　　Wireless systems-on-chip (SoCs) are favored by IoT system designers for their high functionality, low power consumption and space savings. These devices are comprised of a number of key components, including the processors, radios, power management, memory, interfaces and peripherals.　　One of the biggest drivers in wireless SoCs is the growing need for multi-protocol support to meet the requirements of different IoT devices. Chipmakers need to keep up with existing standards that continue to evolve as well as new wireless standards. These include Wi-Fi, Bluetooth LE, Bluetooth classic, 802.15.4, ZigBee, Thread, Z-Wave, Matter, cellular and other proprietary wireless protocols.　　Through this integration and multi-protocol support, wireless SoCs are solving some of the biggest technical challenges around wireless design while simplifying development by providing all of the necessary functionality, along with the connectivity and security in one device. But designers aren’t on their own; SoC makers also provide complete ecosystems and reference designs that can lower design risk and shorten the design cycle.　　“A wireless SoC typically comprises the radio itself—one or more, depending on the application—a MAC/PHY for the Wi-Fi and PHY for Bluetooth, along with a power management unit, memory, various I/O ports, a debug port, possibly an analog-to-digital converter and bus management IP,” said Brandon Bae, senior director of product marketing for wireless connectivity at Synaptics Incorporated. “Interfaces for external power amplifier and low-noise amplifier options, with associated switches, are also good to have.”　　Brandon Bae, senior director, product marketing, wireless connectivity at Synaptics Incorporated.　　Depending on the protocols supported and the end applications, the components in a wireless SoC could be different, said Dhiraj Sogani, senior director of wireless product marketing at Silicon Labs. “Power optimization, longer range, robust connectivity, higher processing power, more peripherals and higher memory will continue to be the driving trends in wireless SoCs, and we will see continuous improvement in these.”　　Wireless SoCs are also packed with security features, making them suited for a range of embedded IoT systems, such as smart homes, smart metering, building automation and fitness devices.　　“Security is increasingly a concern to protect personal data and to protect IP, and many SoCs are adding features to address security at multiple hardware and software levels,” said Nathalie Vallespin, wireless product line marketing manager at STMicroelectronics.　　Highly integrated wireless SoCs　　As demand grows for wireless SoCs, chipmakers continue to meet requirements for better security and greater interoperability and are adding advanced features for sensors, graphics, artificial intelligence and machine learning. There is also a drive toward multi-protocol connectivity support with options for Wi-Fi, Bluetooth, LoRa, Zigbee, Matter and other protocols.　　“There is always a requirement for a higher level of integration in the wireless SoCs to meet the application use cases, simplify IoT device development and reduce cost,” Sogani said.　　One of the key areas is a higher level of hardware and software integration, which includes the integrated applications processor, integrated networking stacks, cloud connectivity, digital and analog peripherals, additional GPIOs and higher memory, along with support for new protocols like Matter, Amazon Sidewalk and Wi-SUN, he added.　　“Integration of multiple protocols is becoming critical,” Sogani said. These include the combinations of Wi-Fi and BLE and 802.15.4 and BLE, as well as Wi-Fi, BLE, 802.15.4 and even sub-gigahertz integration.　　“Bluetooth classic integration is also needed to support legacy headsets,” he added. “These protocols need to operate concurrently, which needs significant hardware and software work.”　　Dhiraj Sogani, senior director, wireless product marketing, at Silicon Labs.　　In addition, “Matter over Thread and Matter over Wi-Fi is gaining significant momentum, as it enables interoperability of different ecosystems, such as Google, Amazon and Samsung,” Sogani said. “Wi-SUN is becoming more critical for smart-city deployments. Amazon Sidewalk shows significant promise to become a leading protocol for neighborhood connectivity.”　　Vallespin noted that the evolution in standards is also enabling new use cases: “In Bluetooth Low Energy, audio is creating many new use cases to manage new user experiences and is replacing the Bluetooth classic technology. Matter technology, just announced late last year, is a new standard for connected-home applications, and ultra-wideband is increasingly being used for car access control.”　　STMicroelectronics offers a wireless roadmap based on its popular STM32 family of microcontrollers and ecosystem. These include the STM32WB series for Bluetooth LE, Thread, Matter and Zigbee and the STM32WL for LoRa and other sub-gigahertz protocols. “STM32 wireless products add best-in-class IPs to smoothly migrate to wireless platforms,” Vallespin said.　　Sogani noted two other key trends, including the integration of machine learning for IoT edge devices for simple audio, vision and data applications like keyword spotting, motion detection and glass-break detection, as well as security integration at the hardware and software level for improving IoT device security.　　Synaptics’ Bae agreed that there is a higher degree of integration coming: “We’re looking at advancing to finer nodes to not only shrink the die size, but it also frees up space to integrate more memory for more features for a given package size. The drivers tend to be functionality, size, power and cost, so if we can provide greater functionality for a given footprint while also improving power consumption, our customers like that.　　“It’s not always good to move to a smaller package, even when that’s possible, as that requires board redesigns,” Bae said. “More functionality is often preferred.”　　Similarly, Vallespin said the process node is a key factor in delivering new degrees of integration. “Smaller geometries allow greater integration.”　　Latest advances　　Wireless SoC vendors agreed that new product development is driven by wireless standards and the need for higher functionality, more integration and lower power consumption.　　For example, Silicon Labs’ wireless SoC roadmap focuses on “intelligent wireless connectivity for IoT devices.” The company offers a wide range of wireless solutions, including Wi-Fi, Bluetooth, 802.15.4, ZigBee, Thread, Z-Wave and proprietary wireless.　　Silicon Labs’ latest advances include its 2.4-GHz wireless MG24 SoC for Bluetooth and multiple-protocol operations. The MG24 supports Matter over Thread as a single-chip solution—with a range of up to 200 meters indoors for OpenThread—while also enabling Bluetooth commissioning of new devices on the same chip, Sogani said. “The MG24, combined with the ultra-low–power Silicon Labs RS9116 or Silicon Labs WF200 Wi-Fi products, enables development of Matter over Wi-Fi 4.”　　Silicon Labs also offers the FG25, the company’s new flagship SoC for Wi-SUN, which is one of the world’s first open protocols for smart-city and smart-utility applications. “The EFF01 is the FG25’s corresponding amplifier that boosts signal range by 2× when used together,” Sogani said.　　He said the FG25 “will be the world’s most secure smart-city solution, with long range, the largest memory capacity of any SoC in the Silicon Labs portfolio and the ability to operate for up to 10 years on a coin-cell battery.”　　In addition, Silicon Labs’ first Wi-Fi 6 and Bluetooth LE SoC, the fully integrated SiWx917, is designed to be the lowest-power Wi-Fi 6 and Bluetooth LE SoC in the industry, Sogani said. “The SiWx917 is a single-chip solution that is Matter-ready, includes an integrated applications processor and offers industry-leading energy efficiency, making it ideal for battery-powered or energy-efficient IoT devices with always-on cloud connectivity.”　　Synaptics is focusing on two major industry trends: connecting sensors that are gathering data to the AI systems or devices that are doing the analysis, and making wireless devices easier to use, Bae said.　　“First, we’re simplifying the integration of AI and wireless through KatanaConnect, which combines our Katana low-power edge AI SoC with our SYN430132 1 × 1 Wi-Fi/Bluetooth combo chip on a tiny module measuring 32 × 32 mm,” he said. “Second, our mix of Bluetooth, ULE, Wi-Fi, 802.15.4 and GNSS solutions is unique in the industry. They are proven solutions that simplify the cost-effective and rapid development of IoT connectivity devices. This has clear single-source benefits of both product and design expertise, so we know how to connect IoT devices.”　　However, Bae said there is more to it than having the silicon and track record. “We’re also either already Matter-compliant or are working on it across all our solution stacks so we can ensure users benefit from Matter’s promise of a seamless user experience across platforms and interfaces.”　　A good example of Synaptics’ Matter support and high integration is the SYN4381 Triple Combo SoC, which the company claims as the first to combine Wi-Fi 6/6E (802.11ax with extended 6-GHz operation), Bluetooth 5.2 (BT 5.2) with BLE audio and high-accuracy distance measurement, and IEEE 802.15.4 with built-in support for the Thread protocol and Matter application layer. The SoC and its SynFi software simplify product development by providing secure and scalable connectivity between devices across heterogeneous IoT networks, regardless of platform, OEM or brand, the company said. For end users, they get a simplified setup and seamless control across their smart-home devices.　　Key differentiators for Synaptics include its robust connectivity and the ability to balance cost and performance, Bae said. “For example, while many offer Wi-Fi/Bluetooth combo solutions, they haven’t fully controlled the signaling, and that shows up as glitches in both audio and video.”　　To solve the problem, Synaptics has developed a proprietary mechanism, which it calls Smart Coexistence, in the 2.45-GHz band. It “carefully manages the Wi-Fi and Bluetooth transmission and reception to avoid lost packets and the inefficiencies of retransmissions,” Bae said.　　Bae added it is baked into all of its combo chips, including the SYN4381 Triple Combo, as well as the SYN43756 Bluetooth/Wi-Fi combo chip, an IEEE 802.11ax 2 × 2 MAC/baseband/radio IC with integrated Bluetooth 5.2 (with LE Audio).

Key word：

Wireless,SoC,IoT

Release time：2023-02-23 15:59 reading：1920 Continue reading>>

Adding NoCs To FPGA <span style='color:red'>SoCs</span>

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Adding NoCs To FPGA SoCs

　　FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are facing some of the same issues as standard SoCs, including the ability to move larger and larger amounts of data quickly throughout an increasingly complex device, and the difficulty in verifying and debugging any problems that might show up along the way.　　FPGA SoCs are a hybrid device, and they are gaining traction as chipmakers and systems companies are tasked with completing more designs per year, often in markets where protocols and algorithms are still in flux, such as automotive, medical devices and security. Using a standard FPGA chip can provide the necessary flexibility, but only an ASIC can meet the higher performance requirements, both for new and existing markets such as aerospace. FPGA SoCs offer a compromise solution that basically splits the difference, providing some of the performance and low-power benefits of an ASIC and the flexibility to avoid early obsolescence.　　But this level of complexity also adds issues that are very familiar to SoC design teams.　　“The complexity and capabilities of FPGA have grown so much that you can build big systems with multiple interfaces and protocols in a single FPGA, and such designs require a fabric to integrate different IP and hardware modules working at various clock domains and data protocols,” said Zibi Zalewski, general manager for Aldec’s Hardware Division.　　Modern FPGAs — especially those with hard embedded processors and controllers — fit somewhere between traditional logic FPGAs and ASICs, with a nod to the ASIC direction. “A NoC is definitely needed, because having a NoC simplifies the interfacing from the verification point of view,” Zalewski said. “A NoC in the design allows the engineering team to manage the top-level interfacing, which can be further used to create a main prototyping channel to the host computer or a transactor for emulation, instead of multiple interfaces that increase the complexity, time and cost of the verification process.”　　This has some interesting implications for FPGA SoC tooling. FPGA vendors generally sell their own tools with their hardware, which has made it difficult for EDA vendors to make a significant dent in that market. But as these two worlds begin to merge, there are questions about whether the kind of complex tooling and IP that makes a finFETpossible, for example, also may be required inn an FPGA SoC—particularly in safety critical applications where traceability is required.　　“When using high-capacity FPGAs for design verification and prototyping purposes, one of the key requests is for appropriate debug capabilities,” said Juergen Jaeger, product management director at Cadence. “However, the architecture in today’s no-NoC FPGAs makes it challenging to provide such debug features, mostly due to finite (limited) connectivity resources in the FPGA, especially as all the FPGA-internal routing resources are needed to implement the design itself and run it at sufficient-enough performance. Also, debug requires being able to access as many internal design nodes as possible, ideally all, and route those probe points to the outside. This is almost impossible, and results in many challenges and debug shortcomings. This is where an FPGA-internal NoC could help, as it would provide the ability to probe many nodes locally, route the data through the NoC to an aggregator without wasting precious FPGA routing resources, and then export the debug data through some standard interface, such as gigabit Ethernet, to the outside world.”　　Not all FPGAs will need NoCs, however. “It might help if the design is a data-path heavy design, moving a lot of data around,” Jaeger said. “However, if the design is more control-centric, and/or requires the highest possible performance, the inherent latency and non-deterministic nature of a NoC might be counterproductive. It will also require new FPGA design tools that can take advantage of a NoC component inside an FPGA.”　　Lower power　　ASICs inherently are more power-efficient than FPGAs. Now the question is how much power overhead can be shaved off by combining these devices and utilizing some of the low-power techniques that have been developed for SoCs, such as more efficient signal routing through a NoC.　　“The NoC enables FPGA resources to be shared by IP cores and external interfaces and facilitates power management techniques,” said Aldec’s Zalewski. “With a NoC, the FPGA logic can be divided into regions, each of which can be handled by individual NoC nodes called routers and turned off selectively into sleep mode if not used.”　　This notion of flexibility is what drove the formation of the CCIXConsortium, which was founded to enable a new class of interconnect focused on emerging acceleration applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology.　　The standard is meant to allow processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to a number of acceleration devices including FPGAs, GPUs, network/storage adapters, intelligent networks and custom ASICs.　　This is especially key when using FPGA to accelerate a workload. Anush Mohandass, vice president of marketing at NetSpeed Systems, noted that during the Hot Chip conference a few years ago, Microsoft said it wanted to accelerate image search in Bing using FPGAs rather than running it in a regular server. “They found higher efficiency and lower latency using FPGA acceleration for images, so that’s a place where FPGAs can come into the forefront. Instead of using it as a general-purpose compute, you use it for acceleration.”　　In fact, Mohandass suggests this is the genesis behind the CCIX moment. “Even when Microsoft did it and said, ‘We have the Xeon processor, that’s the main CPU, that’s the main engine — when it detects something that the FPGA can do, it offloads it to the FPGA. If that is the case, why should you treat the accelerator as a second-class citizen? In CCIX, acceleration literally has the same privileges as your core compute cluster.”　　There are other technical issues with today’s advanced FPGAs that may benefit from the structure of a NoC, as well.　　“Each FPGA fabric can look like an SoC just in terms of sheer gate count and complexity,” said Piyush Sancheti, senior director of marketing at Synopsys. “But now that you have all this real estate available, you’re obviously jamming more function into a single device, and that’s creating multifunctional complexity as well as things like clocking. We see that clocking structures in FPGAs are becoming much more complex, which creates a whole bunch of new issues.”　　IP reuse　　This simplifies design reuse, as well. “Typically, if the design is in any kind of a SoC environment, whether that’s implemented on ASIC or FPGA, the more IPs that are integrated, the more asynchronous clocks there are in the design,” Sancheti said. “There may be a PCIe running at 66 MHz, there may be other aspects of the design that are running at a much higher frequency, and these by design are not synchronous with each other. What that means, essentially, is that there is logic operating at different frequencies, but this logic is communicating with each other. This causes clock domain crossing issues. How do you make sure that when a signal goes from a fast clock domain to slow, and vice versa, that the signal is reliable, and that you don’t have meta stable signals, where essentially the timing of those signals is not completely synchronized?”　　Just like an SoC design, a very complex synchronization scheme is needed, along with the tools and methodologies to ensure the proper synchronization is in place. “Everybody who’s doing anything more than jelly bean FPGAs has a complete methodology around the clock domain crossing verification, which is actually somewhat new to the FPGA design community,” he said. “If you map all of these challenges to design flows and methodologies, there are new things being added to their flows that historically they didn’t need to worry about purely because they didn’t have that many IPs and they didn’t have that many clock domains to deal with. It goes back to the simplicity of the design and the end application. As FPGAs become more SoC-like, unfortunately they have to deal with all the challenges of doing SoC design.”　　Bridging the gap　　So are today’s FPGA SoCs enough like traditional, digital SoCs that all the same rules apply for a network on chip? The answer appears to be somewhat, but not completely.　　“Both of the main FPGA vendors have proprietary network-on-chip tools, and if a user chooses to use one of those, they can hook up their functions using a form of network on chip,” said Ty Garibay, CTO of ArterisIP. “It is more of a conceptual approach to the system. Does it look enough like a standard SoC that it makes more sense to think of it as having a NoC as the connectivity backbone? Many FPGA applications do not. They look a lot more like a networking chips or backbone chips that are fundamentally data flow. Data comes in the left, you have a whole bunch of a munging units, and data goes out the right. That is not a traditional SoC. That’s a normal network processor or baseband modem or something like that, where it’s a data flow chip. So in those types of FPGA soft designs, there’s no need for a network on chip.”　　But if it conceptually looks like a bunch of independent functional units that communicate with each other and are controlled generally by a central point, then it does make sense to have those connected with a soft network on chip, he said. “The next generation of high-performance of FPGAs are expected to contain hard NoCs built into the chip because they are getting to the point where the data flow is at such a high rate—especially when you have 100-gigabit SerDes and HBM2, where trying to pipe a terabit or two per channel through soft logic essentially uses all the soft logic and you’ve got nothing left to be processing with.”　　As a result, that bandwidth is going to require a hardening of the data movement that is enforced in much the same way that processing enforces hard DSPs or hard memory controllers. Successive generations of FPGAs may be expected to look like a checkerboard of streets, where the streets are hard 128, 256, 512 12-bit buses that go from end to end in one or two cycles and don’t use up any soft logic to do it.　　“Along with this would be the synthesis function that allocates on-ramps and off-ramps to those channels as part of hardening the function onto the FPGAs, because we’re moving so much data around I just don’t see how they can continue to do that in soft logic,” Garibay said. “That will be the coming of real NoCs onto FPGAs, because NoCs are always a good idea.”

Key word：

NoCs,SoCs

Release time：2018-07-03 00:00 reading：1216 Continue reading>>

Q’comm Details ARM Server <span style='color:red'>SoCs</span>

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Q’comm Details ARM Server SoCs

　　Qualcomm will describe the custom ARM core inside its first server processor at Hot Chips this week. The Falkor CPU is at the heart of the company’s 10-nm Centriq 2400, a 48-core SoC that will ship later this year, targeting big data centers.　　To date, a handful of companies have tried to gain footholds in servers with ARM-based products. They have generally failed so far because their parts could not match the performance of Intel’s x86-based Xeon. However, earlier this year Microsoft’s data center group announced it is testing SoCs from Qualcomm and rival Cavium.　　It’s still unclear how Qualcomm will fare. The company did not provide any performance, power consumption or price information on its parts.　　The ARM chips debut at a moment of unusually high competition. AMD just started shipping Epyc, its x86 server SoC with up to 32 cores, while Intel just refreshed Xeon with its Skylake architecture. Both are made in 14-nm processes.　　Perhaps the most interesting disclosure about the 64-bit Falkor is it consists of two custom ARMv8 cores. Thus, the 48-core Centriq is actually made up of 24 dual-core processors running at about 1V.b　　The dual-core approach is roughly similar to one used by AMD’s Bulldozer, a 2010 x86 core that struggled to compete with rival Intel. The dual Qualcomm CPUs share an L2 cache and ring interconnect with more than 250 GBytes/second aggregate bandwidth.　　Each out-of-order Falkor core can dispatch up to three instructions and one direct branch per cycle. They use a pipeline that supports 128-bit loads and stores and varies in length depending on the operation.　　The cores and L2 caches can run at independent power states. They are managed by a block head switch or low-dropout regulator from a shared supply rail that acts as a hardware state machine speeding state transitions.　　While the dual cores share one L2 caches in each block, the L3 is a central cache running on the SoC’s ring bus. Qualcomm did not provide sizes of the caches.　　The SoC supports six DDR4 channels at 2,667 MTransfers/s and 32 PCI Express Gen 3 lanes. AMD bests both Qualcomm and Intel providing eight DDR4 channels and 128 PCIe Gen 3 lanes on Epyc.　　The Centriq incudes a south bridge block supporting SATA, USB and other I/Os. The chip fits in a 55mm2 LGA package.　　The SoC supports ARM’s virtualization, TrustZone security and instruction extensions to accelerate crypto operations. In addition, it stores boot load and authentication code in an integrated ROM.

Key word：

Q’comm,ARM,SoCs

Release time：2017-08-22 00:00 reading：1315 Continue reading>>

ARM <span style='color:red'>SoCs</span> Take Soft Roads to Neural Nets

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ARM SoCs Take Soft Roads to Neural Nets

　　NXP is supporting inference jobs such as image recognition in software on its i.MX8 processor. It aims to extend its approach for natural-language processing later this year, claiming that dedicated hardware is not required in resource-constrained systems.　　The chip vendor is following in the footsteps of its merger partner, Qualcomm. However, the mobile giant expects to eventually augment its code with dedicated hardware. Their shared IP partner, ARM, is developing neural networking libraries for its cores, although it declined an interview for this article.　　NXP’s i.MX8 packs two GPU cores from Vivante, now part of Verisilicon. They use about 20 opcodes that support multiply-accumulates and bit extraction and replacement, originally geared for running computer vision.　　“Adding more and more hardware is not the way forward on the power budget of a 5-W SoC,” said Geoff Lees, NXP’s executive vice president for i.MX. “I would like to double the Flops, but we got the image processing acceleration we wanted for facial and gesture recognition and better voice accuracy.”　　The software is now in use with NXP’s lead customers for image-recognition jobs. Meanwhile, Verisilicon and NXP are working on additional extensions to the GPU shader pipeline targeting natural-language processing. They hope to have the code available by the end of the year.　　“Our VX extensions were not originally viewed as a neural network accelerator, but we found [that] they work extraordinarily well … the math isn’t much different,” said Thomas “Rick” Tewell, vice president of system solutions at Verisilicon.　　The GPU cores come with OpenCL drivers. “No one has to touch the instruction extensions … people don’t want to get locked into an architecture or tool set; they want to train a set of engineers who are interchangeable.”　　ARM is taking a similar approach with its ARM Compute Library, released in March to run neural net tasks on its Cortex-A and Mali cores.　　“It doesn’t have a lot of features yet and only supports single-precision math — we’d prefer 8-bit — but I know ARM is working on it,” said a Baidu researcher working on its neural net benchmark. “It also lacks support for recurrent neural nets, but most libraries still lack this.”　　For its part, Qualcomm released earlier this year its Snapdragon 820 Neural Processing Engine SDK. It supports jobs run on the SoC’s CPU, GPU, and DSP and includes Hexagon DSP vector extensions to run 8-bit math for neural nets.　　“Long-term, there could be a need for dedicated hardware,” said Gary Brotman, director of product management for commercial machine-learning products at Qualcomm. “We have work in the lab today but have not discussed a time-to-market.”　　The code supports a variety of neural nets, including LSTMs often used for audio processing. Both NXP and Qualcomm execs said that it’s still early days for availability of good data sets to train models for natural-language processing. “Audio is the next frontier,” said Brotman.

Key word：

ARM,SoCs,Neural Nets

Release time：2017-06-30 00:00 reading：1134 Continue reading>>

AMD Rolls Epyc Server <span style='color:red'>SoCs</span>

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AMD Rolls Epyc Server SoCs

　　Advanced Micro Devices showed as many as two dozen systems using Epyc 7000, the server processor family it released today. The launch reignites competition in one of the most lucrative sectors of Intel’s x86 business.　　AMD announced nine Epyc processors, using its Zen x86 core to deliver 23–70% more performance than Intel’s 14-nm Broadwell parts across a range of benchmarks. All support eight 2,666-MHz DDR 4 channels and 128 PCI Express Gen 3 lanes, compared to about four memory channels and 40 PCIe lanes in the average Xeon.　　The chips arrive as Intel is about to roll out its first 10-nm Xeon chips based on its Skylake architecture. Some Epyc parts “could still be ahead of Intel’s coming generation, but not as much,” said Nathan Brookwood, principal of market watcher Insight64.　　“AMD’s Epyc has a very real opportunity to disrupt Intel’s two-socket server cash machine,” said Kevin Krewell, senior analyst at Tirias Research. “Intel has controlled that market well and has been able to protect its position while slowly increasing its ASPs.”　　The dual-threaded Epyc processors range from eight-core chips drawing 120 W at 2.1 GHz to 32-core chips drawing 180 W at 2.2 GHz. Because of their hefty complement of memory and I/O, a single-socket Epyc server may be adequate for some users who needed two-socket Xeon servers.　　“Intel artificially constrained what they do with a single socket, so if you needed a lot of memory and I/O, you needed two Xeon chips,” said Brookwood.　　The new chips cover the current Xeon price range from $400 to $4,000, with AMD aiming to give users more performance at existing price points. They use four small die in a system-in-package, enabling higher yields and, thus, lower costs than Intel’s generally larger monolithic chips.　　An Intel spokesman said the company expects with its upcoming Skylake family "to continue offering the highest core and system performance versus AMD. AMD’s approach of stitching together four desktop die in a processor is expected to lead to inconsistent performance and other deployment complexities in the data center.”　　The chips are AMD’s second major volley in renewed x86 competition with Intel. It announced high-end desktop chips in February and, later this year, is expected to announce notebook versions.

Key word：

AMD,SoCs

Release time：2017-06-21 00:00 reading：1631 Continue reading>>

Intel Sued Over Handset <span style='color:red'>SoCs</span>

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Intel Sued Over Handset SoCs

　　A computer company based in Brazil is suing Intel Corp., claiming its SoFia SoC caused smartphones to overheat, catch fire and explode. Qbex Computadores SA filed suit June 12 in San Jose District Court claiming up to $100 million in damages.　　In its complaint, Qbex claims it received 35,000 customer complaints and 4,000 lawsuits in Brazil due to design errors found in the SoFia SoC by an independent review it plans to release later. Qbex “is now known as the brand of exploding and defective smartphones,” it said.　　Intel initially declined to comment on the complaint, a copy of which a Qbex attorney sent to EE Times. Intel co-developed the SoFia SoCs with China’s RockChip but discontinued it in April 2016 as part of a reorg of its struggling mobile business group.　　Later, an Intel spokeswoman said, “We are reviewing the allegations in the complaint and we will investigate them thoroughly. However, we have no evidence to suggest that the overheating issues Qbex alleges were caused by our product.”　　Qbex got its start as an electronics assembler in 2003. It rose to annual sales of $85 million, selling as many as 600,000 desktop PCs in 2012. It moved into tablets and in 2015 sold Brazil’s second most popular system next to the Samsung Galaxy, the complaint said.　　In June 2015, Qbex struck a deal with Intel to assemble and sell smartphones using on the SoFia SoC and other components provided by a group of four contract manufacturers in China. It had also considered a smartphone deal with Qualcomm.　　At one point Qbex shifted more than 90 percent of its assembly operations to SoFia smartphones and hired 200 people to support the business. It sold a total of 235,074 units between October 2015 and December 2016 before ending the business amid rapidly rising customer complaints.　　Qbex charged Intel and its contract manufacturers failed to inform it of design problems with SoFia. It also charged Intel tried to sell it as many as 1.25 million SoFia chips in May 2016, after it discontinued the business.　　Ultimately Qbex hired as many as 216 people just to deal with complains and suits regarding the handsets and agreed to exchange 18,000 units.

Key word：

Intel,SoCs

Release time：2017-06-14 00:00 reading：1171 Continue reading>>

model	brand	Quote
RB751G-40T2R	ROHM Semiconductor
CDZVT2R20B	ROHM Semiconductor
MC33074DR2G	onsemi
BD71847AMWV-E2	ROHM Semiconductor
TL431ACLPR	Texas Instruments

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ESR03EZPJ151	ROHM Semiconductor
BU33JA2MNVX-CTL	ROHM Semiconductor
IPZ40N04S5L4R8ATMA1	Infineon Technologies
BP3621	ROHM Semiconductor
STM32F429IGT6	STMicroelectronics
TPS63050YFFR	Texas Instruments

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